Commit a00e8571 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Update DML2.1 generated code 



Most of the DML code is generated, and it is necessary to update some
parts of it from time to time. This commit brings the latest generated
code for DML 2.1.

Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 91b586cc

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+14 −5
Original line number Diff line number Diff line
@@ -338,7 +338,8 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in 
}



static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,

		struct dc_stream_state *stream)

		struct dc_stream_state *stream,

		struct dml2_context *dml_ctx)

{

	unsigned int hblank_start, vblank_start;
@@ -372,7 +373,12 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf 
	timing->drr_config.drr_active_variable = stream->vrr_active_variable;

	timing->drr_config.drr_active_fixed = stream->vrr_active_fixed;

	timing->drr_config.disallowed = !stream->allow_freesync;

	//timing->drr_config.max_instant_vtotal_delta = timing-><drr no flicker delta lum>;



	if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&

			stream->ctx->dc->config.enable_fpo_flicker_detection == 1)

		timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);

	else

		timing->drr_config.max_instant_vtotal_delta = 0;



	if (stream->timing.flags.DSC) {

		timing->dsc.enable = dml2_dsc_enable;
@@ -505,7 +511,8 @@ static void populate_dml21_stream_overrides_from_stream_state( 
		stream_desc->overrides.odm_mode =  dml2_odm_mode_auto;

		break;

	}

	if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy)

	if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy ||

			stream->debug.force_odm_combine_segments > 0)

		stream_desc->overrides.disable_dynamic_odm = true;

	stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp;

}
@@ -699,7 +706,7 @@ static const struct scaler_data *get_scaler_data_for_plane( 
			temp_pipe->stream = pipe->stream;

			temp_pipe->plane_state = pipe->plane_state;

			temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;



			temp_pipe->stream_res = pipe->stream_res;

			dml_ctx->config.callbacks.build_scaling_params(temp_pipe);

			break;

		}
@@ -956,7 +963,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s 
			disp_cfg_stream_location = dml_dispcfg->num_streams++;



		ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);

		populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index]);

		populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);

		populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);

		populate_dml21_stream_overrides_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index]);
@@ -1007,6 +1014,8 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state 
	context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.dcfclk_khz;

	context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.uclk_khz;

	context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.fclk_khz;

	context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.idle.uclk_khz;

	context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.idle.fclk_khz;

	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.deepsleep_dcfclk_khz;

	context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming->fclk_pstate_supported;

	context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported;

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_contex 
	pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||

			in_dc->debug.force_disable_subvp ||

			disable_fams2;

	pmo_options->disable_drr_fixed = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||

	pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||

			disable_fams2;

	pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||

			disable_fams2;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h

+20 −7
Original line number Diff line number Diff line
@@ -120,11 +120,11 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = { 
				.num_clk_values = 2,

		},

		.phyclk_d18 = {

				.clk_values_khz = {667000, 667000},

				.clk_values_khz = {625000, 625000},

				.num_clk_values = 2,

		},

		.phyclk_d32 = {

				.clk_values_khz = {2000000, 2000000},

				.clk_values_khz = {625000, 625000},

				.num_clk_values = 2,

		},

		.dram_config = {
@@ -289,17 +289,29 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = { 
		.dram_clk_change_blackout_us = 400,

		.fclk_change_blackout_us = 0,

		.g7_ppt_blackout_us = 0,

		.stutter_enter_plus_exit_latency_us = 21,

		.stutter_exit_latency_us = 16,

		.stutter_enter_plus_exit_latency_us = 54,

		.stutter_exit_latency_us = 41,

		.z8_stutter_enter_plus_exit_latency_us = 0,

		.z8_stutter_exit_latency_us = 0,

		/*

		.g6_temp_read_blackout_us = {

			23.00,

			10.00,

			10.00,

			8.00,

			8.00,

			5.00,

			5.00,

			5.00,

		},

		*/

	},



	 .vmin_limit = {

		.dispclk_khz = 600 * 1000,

	 },



	.dprefclk_mhz = 700,

	.dprefclk_mhz = 720,

	.xtalclk_mhz = 100,

	.pcie_refclk_mhz = 100,

	.dchub_refclk_mhz = 50,
@@ -309,8 +321,8 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = { 
	.return_bus_width_bytes = 64,

	.hostvm_min_page_size_kbytes = 0,

	.gpuvm_min_page_size_kbytes = 256,

	.phy_downspread_percent = 0,

	.dcn_downspread_percent = 0,

	.phy_downspread_percent = 0.38,

	.dcn_downspread_percent = 0.38,

	.dispclk_dppclk_vco_speed_mhz = 4500,

	.do_urgent_latency_adjustment = 0,

	.mem_word_bytes = 32,
@@ -329,6 +341,7 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = { 
	.max_num_dp2p0_outputs = 4,

	.rob_buffer_size_kbytes = 192,

	.config_return_buffer_size_in_kbytes = 1344,

	.config_return_buffer_segment_size_in_kbytes = 64,

	.meta_fifo_size_in_kentries = 22,

	.compressed_buffer_segment_size_in_kbytes = 64,

	.subvp_drr_scheduling_margin_us = 100,

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

+7 −2
Original line number Diff line number Diff line
@@ -380,7 +380,11 @@ struct dml2_plane_parameters { 
		enum dml2_refresh_from_mall_mode_override refresh_from_mall;

		unsigned int det_size_override_kb;

		unsigned int mpcc_combine_factor;

		long reserved_vblank_time_ns; // 0 = no override, -ve = no reserved time, +ve = explicit reserved time



		// reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait

		// The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override.

		long reserved_vblank_time_ns;

		unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay

		unsigned int gpuvm_min_page_size_kbytes;



		enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config
@@ -407,6 +411,7 @@ struct dml2_stream_parameters { 
		enum dml2_odm_mode odm_mode;

		bool disable_dynamic_odm;

		bool disable_subvp;

		bool disable_fams2_drr;

		int minimum_vblank_idle_requirement_us;

		bool minimize_active_latency_hiding;
@@ -429,7 +434,7 @@ struct dml2_display_cfg { 
	bool minimize_det_reallocation;



	unsigned int gpuvm_max_page_table_levels;

	unsigned int hostvm_max_page_table_levels;

	unsigned int hostvm_max_non_cached_page_table_levels;



	struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];

	struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h

+3 −0
Original line number Diff line number Diff line
@@ -169,8 +169,11 @@ struct dml2_ip_capabilities { 
	unsigned int max_num_dp2p0_outputs;

	unsigned int rob_buffer_size_kbytes;

	unsigned int config_return_buffer_size_in_kbytes;

	unsigned int config_return_buffer_segment_size_in_kbytes;

	unsigned int meta_fifo_size_in_kentries;

	unsigned int compressed_buffer_segment_size_in_kbytes;

	unsigned int max_flip_time_us;

	unsigned int hostvm_mode;

	unsigned int subvp_drr_scheduling_margin_us;

	unsigned int subvp_prefetch_end_to_mall_start_us;

	unsigned int subvp_fw_processing_delay;