Commit a01486dc authored by David E. Box's avatar David E. Box Committed by Hans de Goede
Browse files

platform/x86/intel/pmc: Cleanup SSRAM discovery 



Clean up the code handling SSRAM discovery. Handle all resource allocation
and cleanup in pmc_core_ssram_get_pmc(). Return the error status from this
function but only fail the init if we fail to discover the primary PMC.

Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20231129222132.2331261-14-david.e.box@linux.intel.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 9512920a

drivers/platform/x86/intel/pmc/core_ssram.c

+33 −29
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 *

 */



#include <linux/cleanup.h>

#include <linux/pci.h>

#include <linux/io-64-nonatomic-lo-hi.h>
@@ -21,6 +22,8 @@ 
#define SSRAM_IOE_OFFSET	0x68

#define SSRAM_DEVID_OFFSET	0x70



DEFINE_FREE(pmc_core_iounmap, void __iomem *, iounmap(_T));



static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid)

{

	for (; list->map; ++list)
@@ -65,44 +68,49 @@ pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, 
	return 0;

}



static void

pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, void __iomem *ssram, u32 offset,

		       int pmc_idx)

static int

pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset)

{

	u64 pwrm_base;

	struct pci_dev *ssram_pcidev = pmcdev->ssram_pcidev;

	void __iomem __free(pmc_core_iounmap) *tmp_ssram = NULL;

	void __iomem __free(pmc_core_iounmap) *ssram = NULL;

	const struct pmc_reg_map *map;

	u64 ssram_base, pwrm_base;

	u16 devid;



	if (pmc_idx != PMC_IDX_SOC) {

		u64 ssram_base = get_base(ssram, offset);

	if (!pmcdev->regmap_list)

		return -ENOENT;



		if (!ssram_base)

			return;

	ssram_base = ssram_pcidev->resource[0].start;

	tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);



	if (pmc_idx != PMC_IDX_MAIN) {

		/*

		 * The secondary PMC BARS (which are behind hidden PCI devices)

		 * are read from fixed offsets in MMIO of the primary PMC BAR.

		 */

		ssram_base = get_base(tmp_ssram, offset);

		ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);

		if (!ssram)

			return;

			return -ENOMEM;



	} else {

		ssram = no_free_ptr(tmp_ssram);

	}



	pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET);

	devid = readw(ssram + SSRAM_DEVID_OFFSET);



	if (pmcdev->regmap_list) {

		const struct pmc_reg_map *map;



	map = pmc_core_find_regmap(pmcdev->regmap_list, devid);

		if (map)

			pmc_core_pmc_add(pmcdev, pwrm_base, map, pmc_idx);

	}

	if (!map)

		return -ENODEV;



	if (pmc_idx != PMC_IDX_SOC)

		iounmap(ssram);

	return pmc_core_pmc_add(pmcdev, pwrm_base, map, PMC_IDX_MAIN);

}



int pmc_core_ssram_init(struct pmc_dev *pmcdev)

{

	void __iomem *ssram;

	struct pci_dev *pcidev;

	u64 ssram_base;

	int ret;



	pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, 2));
@@ -113,18 +121,14 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev) 
	if (ret)

		goto release_dev;



	ssram_base = pcidev->resource[0].start;

	ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);

	if (!ssram)

		goto disable_dev;



	pmcdev->ssram_pcidev = pcidev;



	pmc_core_ssram_get_pmc(pmcdev, ssram, 0, PMC_IDX_SOC);

	pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_IOE_OFFSET, PMC_IDX_IOE);

	pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_PCH_OFFSET, PMC_IDX_PCH);

	ret = pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_MAIN, 0);

	if (ret)

		goto disable_dev;



	iounmap(ssram);

	pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_IOE, SSRAM_IOE_OFFSET);

	pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_PCH, SSRAM_PCH_OFFSET);



	return 0;