Commit a0607951 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull mailbox updates from Jassi Brar:
 "Core:
   - misc cleanup

  sophgo:
   - add driver for CV18XX series

  qcom:
   - add SM7150 APCS compatible
   - apcs: added separate clock node

  imx:
   - fix tx doorbell send

  microchip:
   - misc compile option fix

  mediatek:
   - Refine GCE_GCTL_VALUE setting"

* tag 'mailbox-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
  mailbox: qcom-apcs-ipc: Assign OF node to clock controller child device
  dt-bindings: mailbox: qcom,apcs: Add separate node for clock-controller
  dt-bindings: mailbox: qcom: Add the SM7150 APCS compatible
  mailbox: sophgo: add mailbox driver for CV18XX series SoC
  dt-bindings: mailbox: add Sophgo CV18XX series SoC
  mailbox: Use guard/scoped_guard for spinlock
  mailbox: Use guard/scoped_guard for con_mutex
  mailbox: Remove devm_mbox_controller_unregister
  mailbox: Propagate correct error return value
  mailbox: Not protect module_put with spin_lock_irqsave
  mailbox: Use dev_err when there is error
  mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting
  mailbox: imx: Fix TXDB_V2 sending
  mailbox: mchp-ipc-sbi: Fix COMPILE_TEST build error
parents cd2e103d d0b497df
Loading
Loading
Loading
Loading
+119 −51
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ properties:
              - qcom,qcs615-apss-shared
              - qcom,sc7180-apss-shared
              - qcom,sc8180x-apss-shared
              - qcom,sm7150-apss-shared
              - qcom,sm8150-apss-shared
          - const: qcom,sdm845-apss-shared
      - items:
@@ -72,6 +73,7 @@ properties:
    description: phandles to the parent clocks of the clock driver
    minItems: 2
    maxItems: 3
    deprecated: true

  '#mbox-cells':
    const: 1
@@ -82,6 +84,23 @@ properties:
  clock-names:
    minItems: 2
    maxItems: 3
    deprecated: true

  clock-controller:
    type: object
    additionalProperties: false
    properties:
      clocks:
        description: phandles to the parent clocks of the clock driver
        minItems: 2
        maxItems: 3

      '#clock-cells':
        enum: [0, 1]

      clock-names:
        minItems: 2
        maxItems: 3

required:
  - compatible
@@ -90,14 +109,19 @@ required:

additionalProperties: false

allOf:
  - if:
# Clocks should be specified either on the parent node or on the child node
oneOf:
  - required:
      - clock-controller
    properties:
        compatible:
          contains:
            enum:
              - qcom,msm8916-apcs-kpss-global
    then:
      clocks: false
      clock-names: false
      '#clock-cells': false
  - properties:
      clock-controller: false

$defs:
  msm8916-apcs-clock-controller:
    properties:
      clocks:
        items:
@@ -107,14 +131,10 @@ allOf:
        items:
          - const: pll
          - const: aux
      '#clock-cells':
        const: 0

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8939-apcs-kpss-global
    then:
  msm8939-apcs-clock-controller:
    properties:
      clocks:
        items:
@@ -126,14 +146,10 @@ allOf:
          - const: pll
          - const: aux
          - const: ref
      '#clock-cells':
        const: 0

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdx55-apcs-gcc
    then:
  sdx55-apcs-clock-controller:
    properties:
      clocks:
        items:
@@ -145,14 +161,10 @@ allOf:
          - const: ref
          - const: pll
          - const: aux
      '#clock-cells':
        const: 0

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq6018-apcs-apps-global
    then:
  ipq6018-apcs-clock-controller:
    properties:
      clocks:
        items:
@@ -164,21 +176,45 @@ allOf:
          - const: pll
          - const: xo
          - const: gpll0
      '#clock-cells':
        const: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8953-apcs-kpss-global
              - qcom,msm8994-apcs-kpss-global
              - qcom,msm8996-apcs-hmss-global
              - qcom,qcm2290-apcs-hmss-global
              - qcom,sdm845-apss-shared
              - qcom,msm8916-apcs-kpss-global
    then:
      $ref: "#/$defs/msm8916-apcs-clock-controller"
      properties:
        clocks: false
        clock-names: false
        clock-controller:
          $ref: "#/$defs/msm8916-apcs-clock-controller"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8939-apcs-kpss-global
    then:
      $ref: "#/$defs/msm8939-apcs-clock-controller"
      properties:
        clock-controller:
          $ref: "#/$defs/msm8939-apcs-clock-controller"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdx55-apcs-gcc
    then:
      $ref: "#/$defs/sdx55-apcs-clock-controller"
      properties:
        clock-controller:
          $ref: "#/$defs/sdx55-apcs-clock-controller"

  - if:
      properties:
@@ -187,11 +223,26 @@ allOf:
            enum:
              - qcom,ipq6018-apcs-apps-global
    then:
      $ref: "#/$defs/ipq6018-apcs-clock-controller"
      properties:
        '#clock-cells':
          const: 1
    else:
        clock-controller:
          $ref: "#/$defs/ipq6018-apcs-clock-controller"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8953-apcs-kpss-global
              - qcom,msm8994-apcs-kpss-global
              - qcom,msm8996-apcs-hmss-global
              - qcom,qcm2290-apcs-hmss-global
              - qcom,sdm845-apss-shared
    then:
      properties:
        clocks: false
        clock-names: false
        clock-controller: false
        '#clock-cells':
          const: 0

@@ -216,6 +267,23 @@ examples:
    };

  # Example apcs with qcs404
  - |
    #define GCC_APSS_AHB_CLK_SRC  1
    #define GCC_GPLL0_AO_OUT_MAIN 123
    mailbox@b011000 {
        compatible = "qcom,qcs404-apcs-apps-global",
                     "qcom,msm8916-apcs-kpss-global", "syscon";
        reg = <0x0b011000 0x1000>;
        #mbox-cells = <1>;

        apcs_clk: clock-controller {
          clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
          clock-names = "pll", "aux";
          #clock-cells = <0>;
        };
    };

  # Example apcs with qcs404 (deprecated: use clock-controller subnode)
  - |
    #define GCC_APSS_AHB_CLK_SRC  1
    #define GCC_GPLL0_AO_OUT_MAIN 123
+60 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo CV1800/SG2000 mailbox controller

maintainers:
  - Yuntao Dai <d1581209858@live.com>
  - Junhui Liu <junhui.liu@pigmoral.tech>

description:
  Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
  shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
  and raise interrupts to receivers. Sending messages to itself is also
  supported.

properties:
  compatible:
    const: sophgo,cv1800b-mailbox

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#mbox-cells":
    const: 2
    description: |
      <&phandle channel target>
      phandle : Label name of mailbox controller
      channel : 0-7, Channel index
      target  : 0-3, Target processor ID

      Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
      <0> Cortex-A53 (Only available on CV181X/SG200X)
      <1> C906B
      <2> C906L
      <3> 8051

required:
  - compatible
  - reg
  - interrupts
  - "#mbox-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    mailbox@1900000 {
        compatible = "sophgo,cv1800b-mailbox";
        reg = <0x01900000 0x1000>;
        interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
        #mbox-cells = <2>;
    };
+12 −2
Original line number Diff line number Diff line
@@ -36,6 +36,16 @@ config ARM_MHU_V3
	  that provides different means of transports: supported extensions
	  will be discovered and possibly managed at probe-time.

config CV1800_MBOX
	tristate "cv1800 mailbox"
	depends on ARCH_SOPHGO || COMPILE_TEST
	help
	  Mailbox driver implementation for Sophgo CV18XX SoCs. This driver
	  can be used to send message between different processors in SoC. Any
	  processer can write data in a channel, and set co-responding register
	  to raise interrupt to notice another processor, and it is allowed to
	  send data to itself.

config EXYNOS_MBOX
	tristate "Exynos Mailbox"
	depends on ARCH_EXYNOS || COMPILE_TEST
@@ -191,8 +201,8 @@ config POLARFIRE_SOC_MAILBOX

config MCHP_SBI_IPC_MBOX
	tristate "Microchip Inter-processor Communication (IPC) SBI driver"
	depends on RISCV_SBI || COMPILE_TEST
	depends on ARCH_MICROCHIP
	depends on RISCV_SBI
	depends on ARCH_MICROCHIP || COMPILE_TEST
	help
	  Mailbox implementation for Microchip devices with an
	  Inter-process communication (IPC) controller.
+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o

obj-$(CONFIG_ARM_MHU_V3)	+= arm_mhuv3.o

obj-$(CONFIG_CV1800_MBOX)	+= cv1800-mailbox.o

obj-$(CONFIG_EXYNOS_MBOX)	+= exynos-mailbox.o

obj-$(CONFIG_IMX_MBOX)	+= imx-mailbox.o
+220 −0
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2024 Sophgo Technology Inc.
 * Copyright (C) 2024 Yuntao Dai <d1581209858@live.com>
 * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
 */

#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kfifo.h>
#include <linux/mailbox_client.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define RECV_CPU		1

#define MAILBOX_MAX_CHAN	8
#define MAILBOX_MSG_LEN		8

#define MBOX_EN_REG(cpu)	(cpu << 2)
#define MBOX_DONE_REG(cpu)	((cpu << 2) + 2)
#define MBOX_SET_CLR_REG(cpu)	(0x10 + (cpu << 4))
#define MBOX_SET_INT_REG(cpu)	(0x18 + (cpu << 4))
#define MBOX_SET_REG		0x60

#define MAILBOX_CONTEXT_OFFSET	0x0400
#define MAILBOX_CONTEXT_SIZE	0x0040

#define MBOX_CONTEXT_BASE_INDEX(base, index) \
	((u64 __iomem *)(base + MAILBOX_CONTEXT_OFFSET) + index)

/**
 * struct cv1800_mbox_chan_priv - cv1800 mailbox channel private data
 * @idx: index of channel
 * @cpu: send to which processor
 */
struct cv1800_mbox_chan_priv {
	int idx;
	int cpu;
};

struct cv1800_mbox {
	struct mbox_controller mbox;
	struct cv1800_mbox_chan_priv priv[MAILBOX_MAX_CHAN];
	struct mbox_chan chans[MAILBOX_MAX_CHAN];
	u64 __iomem *content[MAILBOX_MAX_CHAN];
	void __iomem *mbox_base;
	int recvid;
};

static irqreturn_t cv1800_mbox_isr(int irq, void *dev_id)
{
	struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
	size_t i;
	u64 msg;
	int ret = IRQ_NONE;

	for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
		if (mbox->content[i] && mbox->chans[i].cl) {
			memcpy_fromio(&msg, mbox->content[i], MAILBOX_MSG_LEN);
			mbox->content[i] = NULL;
			mbox_chan_received_data(&mbox->chans[i], (void *)&msg);
			ret = IRQ_HANDLED;
		}
	}

	return ret;
}

static irqreturn_t cv1800_mbox_irq(int irq, void *dev_id)
{
	struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
	u8 set, valid;
	size_t i;
	int ret = IRQ_NONE;

	set = readb(mbox->mbox_base + MBOX_SET_INT_REG(RECV_CPU));

	if (!set)
		return ret;

	for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
		valid = set & BIT(i);
		if (valid) {
			mbox->content[i] =
				MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, i);
			writeb(valid, mbox->mbox_base +
				      MBOX_SET_CLR_REG(RECV_CPU));
			writeb(~valid, mbox->mbox_base + MBOX_EN_REG(RECV_CPU));
			ret = IRQ_WAKE_THREAD;
		}
	}

	return ret;
}

static int cv1800_mbox_send_data(struct mbox_chan *chan, void *data)
{
	struct cv1800_mbox_chan_priv *priv =
		(struct cv1800_mbox_chan_priv *)chan->con_priv;
	struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
	int idx = priv->idx;
	int cpu = priv->cpu;
	u8 en, valid;

	memcpy_toio(MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, idx),
		    data, MAILBOX_MSG_LEN);

	valid = BIT(idx);
	writeb(valid, mbox->mbox_base + MBOX_SET_CLR_REG(cpu));
	en = readb(mbox->mbox_base + MBOX_EN_REG(cpu));
	writeb(en | valid, mbox->mbox_base + MBOX_EN_REG(cpu));
	writeb(valid, mbox->mbox_base + MBOX_SET_REG);

	return 0;
}

static bool cv1800_last_tx_done(struct mbox_chan *chan)
{
	struct cv1800_mbox_chan_priv *priv =
		(struct cv1800_mbox_chan_priv *)chan->con_priv;
	struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
	u8 en;

	en = readb(mbox->mbox_base + MBOX_EN_REG(priv->cpu));

	return !(en & BIT(priv->idx));
}

static const struct mbox_chan_ops cv1800_mbox_chan_ops = {
	.send_data = cv1800_mbox_send_data,
	.last_tx_done = cv1800_last_tx_done,
};

static struct mbox_chan *cv1800_mbox_xlate(struct mbox_controller *mbox,
					   const struct of_phandle_args *spec)
{
	struct cv1800_mbox_chan_priv *priv;

	int idx = spec->args[0];
	int cpu = spec->args[1];

	if (idx >= mbox->num_chans)
		return ERR_PTR(-EINVAL);

	priv = mbox->chans[idx].con_priv;
	priv->cpu = cpu;

	return &mbox->chans[idx];
}

static const struct of_device_id cv1800_mbox_of_match[] = {
	{ .compatible = "sophgo,cv1800b-mailbox", },
	{},
};
MODULE_DEVICE_TABLE(of, cv1800_mbox_of_match);

static int cv1800_mbox_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct cv1800_mbox *mb;
	int irq, idx, err;

	mb = devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL);
	if (!mb)
		return -ENOMEM;

	mb->mbox_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mb->mbox_base))
		return dev_err_probe(dev, PTR_ERR(mb->mbox_base),
				     "Failed to map resource\n");

	mb->mbox.dev = dev;
	mb->mbox.chans = mb->chans;
	mb->mbox.txdone_poll = true;
	mb->mbox.ops = &cv1800_mbox_chan_ops;
	mb->mbox.num_chans = MAILBOX_MAX_CHAN;
	mb->mbox.of_xlate = cv1800_mbox_xlate;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	err = devm_request_threaded_irq(dev, irq, cv1800_mbox_irq,
					cv1800_mbox_isr, IRQF_ONESHOT,
					dev_name(&pdev->dev), mb);
	if (err < 0)
		return dev_err_probe(dev, err, "Failed to register irq\n");

	for (idx = 0; idx < MAILBOX_MAX_CHAN; idx++) {
		mb->priv[idx].idx = idx;
		mb->mbox.chans[idx].con_priv = &mb->priv[idx];
	}

	platform_set_drvdata(pdev, mb);

	err = devm_mbox_controller_register(dev, &mb->mbox);
	if (err)
		return dev_err_probe(dev, err, "Failed to register mailbox\n");

	return 0;
}

static struct platform_driver cv1800_mbox_driver = {
	.driver = {
		.name = "cv1800-mbox",
		.of_match_table = cv1800_mbox_of_match,
	},
	.probe	= cv1800_mbox_probe,
};

module_platform_driver(cv1800_mbox_driver);

MODULE_DESCRIPTION("cv1800 mailbox driver");
MODULE_LICENSE("GPL");
Loading