Commit a08b28c1 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Neil Armstrong
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arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock 



Device-tree expects absent clocks to be specified as <0> (instead of
using <>). This fixes using the FCLK4/FCLK3 clocks as they are now
seen at their correct index (while before they were recognized, but at
the correct index - resulting in the hardware using a different clock
than what the kernel sees).

Fixes: e6884f2e ("arm64: dts: amlogic: g12: switch to the new PWM controller binding")
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250420164801.330505-5-martin.blumenstingl@googlemail.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent 511d388a

arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -2313,7 +2313,7 @@ pwm_ef: pwm@19000 { 
					     "amlogic,meson8-pwm-v2";

				reg = <0x0 0x19000 0x0 0x20>;

				clocks = <&xtal>,

					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <&clkc CLKID_FCLK_DIV4>,

					 <&clkc CLKID_FCLK_DIV3>;

				#pwm-cells = <3>;
@@ -2325,7 +2325,7 @@ pwm_cd: pwm@1a000 { 
					     "amlogic,meson8-pwm-v2";

				reg = <0x0 0x1a000 0x0 0x20>;

				clocks = <&xtal>,

					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <&clkc CLKID_FCLK_DIV4>,

					 <&clkc CLKID_FCLK_DIV3>;

				#pwm-cells = <3>;
@@ -2337,7 +2337,7 @@ pwm_ab: pwm@1b000 { 
					     "amlogic,meson8-pwm-v2";

				reg = <0x0 0x1b000 0x0 0x20>;

				clocks = <&xtal>,

					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */

					 <&clkc CLKID_FCLK_DIV4>,

					 <&clkc CLKID_FCLK_DIV3>;

				#pwm-cells = <3>;