Loading arch/sh/Kconfig.sh64 +7 −18 Original line number Diff line number Diff line Loading @@ -131,22 +131,6 @@ config SH64_PGTABLE_3_LEVEL endchoice choice prompt "HugeTLB page size" depends on HUGETLB_PAGE && MMU default HUGETLB_PAGE_SIZE_64K config HUGETLB_PAGE_SIZE_64K bool "64K" config HUGETLB_PAGE_SIZE_1MB bool "1MB" config HUGETLB_PAGE_SIZE_512MB bool "512MB" endchoice config SH64_USER_MISALIGNED_FIXUP bool "Fixup misaligned loads/stores occurring in user mode" Loading Loading @@ -226,7 +210,12 @@ config PREEMPT bool "Preemptible Kernel (EXPERIMENTAL)" depends on EXPERIMENTAL source "mm/Kconfig" config SH_PCLK_FREQ int "Peripheral clock frequency (in Hz)" default "50000000" source "kernel/Kconfig.hz" source "arch/sh/mm/Kconfig" endmenu Loading Loading @@ -286,7 +275,7 @@ source "fs/Kconfig" source "kernel/Kconfig.instrumentation" source "arch/sh64/Kconfig.debug" source "arch/sh/Kconfig.debug" source "security/Kconfig" Loading arch/sh/mm/Kconfig +7 −3 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ config X2TLB config VSYSCALL bool "Support vsyscall page" depends on MMU depends on MMU && (CPU_SH3 || CPU_SH4) default y help This will enable support for the kernel mapping a vDSO page Loading Loading @@ -175,6 +175,10 @@ config HUGETLB_PAGE_SIZE_64MB bool "64MB" depends on X2TLB config HUGETLB_PAGE_SIZE_512MB bool "512MB" depends on CPU_SH5 endchoice source "mm/Kconfig" Loading Loading @@ -202,12 +206,12 @@ config SH_DIRECT_MAPPED choice prompt "Cache mode" default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) config CACHE_WRITEBACK bool "Write-back" depends on CPU_SH2A || CPU_SH3 || CPU_SH4 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 config CACHE_WRITETHROUGH bool "Write-through" Loading Loading
arch/sh/Kconfig.sh64 +7 −18 Original line number Diff line number Diff line Loading @@ -131,22 +131,6 @@ config SH64_PGTABLE_3_LEVEL endchoice choice prompt "HugeTLB page size" depends on HUGETLB_PAGE && MMU default HUGETLB_PAGE_SIZE_64K config HUGETLB_PAGE_SIZE_64K bool "64K" config HUGETLB_PAGE_SIZE_1MB bool "1MB" config HUGETLB_PAGE_SIZE_512MB bool "512MB" endchoice config SH64_USER_MISALIGNED_FIXUP bool "Fixup misaligned loads/stores occurring in user mode" Loading Loading @@ -226,7 +210,12 @@ config PREEMPT bool "Preemptible Kernel (EXPERIMENTAL)" depends on EXPERIMENTAL source "mm/Kconfig" config SH_PCLK_FREQ int "Peripheral clock frequency (in Hz)" default "50000000" source "kernel/Kconfig.hz" source "arch/sh/mm/Kconfig" endmenu Loading Loading @@ -286,7 +275,7 @@ source "fs/Kconfig" source "kernel/Kconfig.instrumentation" source "arch/sh64/Kconfig.debug" source "arch/sh/Kconfig.debug" source "security/Kconfig" Loading
arch/sh/mm/Kconfig +7 −3 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ config X2TLB config VSYSCALL bool "Support vsyscall page" depends on MMU depends on MMU && (CPU_SH3 || CPU_SH4) default y help This will enable support for the kernel mapping a vDSO page Loading Loading @@ -175,6 +175,10 @@ config HUGETLB_PAGE_SIZE_64MB bool "64MB" depends on X2TLB config HUGETLB_PAGE_SIZE_512MB bool "512MB" depends on CPU_SH5 endchoice source "mm/Kconfig" Loading Loading @@ -202,12 +206,12 @@ config SH_DIRECT_MAPPED choice prompt "Cache mode" default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) config CACHE_WRITEBACK bool "Write-back" depends on CPU_SH2A || CPU_SH3 || CPU_SH4 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 config CACHE_WRITETHROUGH bool "Write-through" Loading