Unverified Commit a0e199ec authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'soc_fsl-6.12-2' of https://github.com/chleroy/linux into soc/drivers 

- A series from Hervé Codina that bring support for the newer version
of QMC (QUICC Multi-channel Controller) and TSA (Time Slots Assigner)
found on MPC 83xx micro-controllers.

- Misc changes for qbman freescale drivers for removing a redundant
warning and using iommu_paging_domain_alloc()

* tag 'soc_fsl-6.12-2' of https://github.com/chleroy/linux: (38 commits)
  soc: fsl: qbman: Remove redundant warnings
  soc: fsl: qbman: Use iommu_paging_domain_alloc()
  MAINTAINERS: Add QE files related to the Freescale QMC controller
  soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware
  soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation
  soc: fsl: qe: Add missing PUSHSCHED command
  soc: fsl: qe: Add resource-managed muram allocators
  soc: fsl: cpm1: qmc: Introduce qmc_version
  soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC
  soc: fsl: cpm1: qmc: Handle RPACK initialization
  soc: fsl: cpm1: qmc: Rename qmc_chan_command()
  soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version
  soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version
  soc: fsl: cpm1: qmc: Re-order probe() operations
  soc: fsl: cpm1: qmc: Introduce qmc_data structure
  dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) QMC controller
  soc: fsl: cpm1: qmc: Add missing spinlock comment
  soc: fsl: cpm1: qmc: Fix 'transmiter' typo
  soc: fsl: cpm1: qmc: Remove unneeded parenthesis
  soc: fsl: cpm1: qmc: Fix blank line and spaces
  ...

Link: https://lore.kernel.org/r/326d9a7d-7674-4c28-aa40-dd2c190244dd@csgroup.eu


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents ec62e2e8 7a99b1c0

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PowerQUICC QE Time-slot assigner (TSA) controller



maintainers:

  - Herve Codina <herve.codina@bootlin.com>



description:

  The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.

  Its purpose is to route some TDM time-slots to other internal serial

  controllers.



properties:

  compatible:

    items:

      - enum:

          - fsl,mpc8321-tsa

      - const: fsl,qe-tsa



  reg:

    items:

      - description: SI (Serial Interface) register base

      - description: SI RAM base



  reg-names:

    items:

      - const: si_regs

      - const: si_ram



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  '^tdm@[0-3]$':

    description:

      The TDM managed by this controller

    type: object



    additionalProperties: false



    properties:

      reg:

        minimum: 0

        maximum: 3

        description:

          The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3

          for TDMd.



      fsl,common-rxtx-pins:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The hardware can use four dedicated pins for Tx clock, Tx sync, Rx

          clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.

          Without the 'fsl,common-rxtx-pins' property, the four pins are used.

          With the 'fsl,common-rxtx-pins' property, two pins are used.



      clocks:

        minItems: 2

        items:

          - description: Receive sync clock

          - description: Receive data clock

          - description: Transmit sync clock

          - description: Transmit data clock



      clock-names:

        minItems: 2

        items:

          - const: rsync

          - const: rclk

          - const: tsync

          - const: tclk



      fsl,rx-frame-sync-delay-bits:

        enum: [0, 1, 2, 3]

        default: 0

        description: |

          Receive frame sync delay in number of bits.

          Indicates the delay between the Rx sync and the first bit of the Rx

          frame.



      fsl,tx-frame-sync-delay-bits:

        enum: [0, 1, 2, 3]

        default: 0

        description: |

          Transmit frame sync delay in number of bits.

          Indicates the delay between the Tx sync and the first bit of the Tx

          frame.



      fsl,clock-falling-edge:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Data is sent on falling edge of the clock (and received on the rising

          edge). If not present, data is sent on the rising edge (and received

          on the falling edge).



      fsl,fsync-rising-edge:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Frame sync pulses are sampled with the rising edge of the channel

          clock. If not present, pulses are sampled with the falling edge.



      fsl,fsync-active-low:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Frame sync signals are active on low logic level.

          If not present, sync signals are active on high level.



      fsl,double-speed-clock:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The channel clock is twice the data rate.



    patternProperties:

      '^fsl,[rt]x-ts-routes$':

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        description: |

          A list of tuple that indicates the Tx or Rx time-slots routes.

        items:

          items:

            - description:

                The number of time-slots

              minimum: 1

              maximum: 64

            - description: |

                The source (Tx) or destination (Rx) serial interface

                (dt-bindings/soc/qe-fsl,tsa.h defines these values)

                 - 0: No destination

                 - 1: UCC1

                 - 2: UCC2

                 - 3: UCC3

                 - 4: UCC4

                 - 5: UCC5

              enum: [0, 1, 2, 3, 4, 5]

        minItems: 1

        maxItems: 64



    allOf:

      # If fsl,common-rxtx-pins is present, only 2 clocks are needed.

      # Else, the 4 clocks must be present.

      - if:

          required:

            - fsl,common-rxtx-pins

        then:

          properties:

            clocks:

              maxItems: 2

            clock-names:

              maxItems: 2

        else:

          properties:

            clocks:

              minItems: 4

            clock-names:

              minItems: 4



    required:

      - reg

      - clocks

      - clock-names



required:

  - compatible

  - reg

  - reg-names

  - '#address-cells'

  - '#size-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/soc/qe-fsl,tsa.h>



    tsa@ae0 {

        compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa";

        reg = <0xae0 0x10>,

              <0xc00 0x200>;

        reg-names = "si_regs", "si_ram";



        #address-cells = <1>;

        #size-cells = <0>;



        tdm@0 {

            /* TDMa */

            reg = <0>;



            clocks = <&clk_l1rsynca>, <&clk_l1rclka>;

            clock-names = "rsync", "rclk";



            fsl,common-rxtx-pins;

            fsl,fsync-rising-edge;



            fsl,tx-ts-routes = <2 0>,             /* TS 0..1 */

                           <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */

                           <1 0>,                 /* TS 26 */

                           <5 FSL_QE_TSA_UCC3>;  /* TS 27..31 */



            fsl,rx-ts-routes = <2 0>,             /* TS 0..1 */

                           <24 FSL_QE_TSA_UCC4>, /* 2..25 */

                           <1 0>,                 /* TS 26 */

                           <5 FSL_QE_TSA_UCC3>;  /* TS 27..31 */

        };

    };

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PowerQUICC QE QUICC Multichannel Controller (QMC)



maintainers:

  - Herve Codina <herve.codina@bootlin.com>



description:

  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one

  serial controller using the same TDM physical interface routed from TSA.



properties:

  compatible:

    items:

      - enum:

          - fsl,mpc8321-ucc-qmc

      - const: fsl,qe-ucc-qmc



  reg:

    items:

      - description: UCC (Unified communication controller) register base

      - description: Dual port ram base



  reg-names:

    items:

      - const: ucc_regs

      - const: dpram



  interrupts:

    maxItems: 1

    description: UCC interrupt line in the QE interrupt controller



  fsl,tsa-serial:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to TSA node

          - enum: [1, 2, 3, 4, 5]

            description: |

              TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these

              values)

               - 1: UCC1

               - 2: UCC2

               - 3: UCC3

               - 4: UCC4

               - 5: UCC5

    description:

      Should be a phandle/number pair. The phandle to TSA node and the TSA

      serial interface to use.



  fsl,soft-qmc:

    $ref: /schemas/types.yaml#/definitions/string

    description:

      Soft QMC firmware name to load. If this property is omitted, no firmware

      are used.



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  '^channel@([0-9]|[1-5][0-9]|6[0-3])$':

    description:

      A channel managed by this controller

    type: object

    additionalProperties: false



    properties:

      compatible:

        items:

          - enum:

              - fsl,mpc8321-ucc-qmc-hdlc

          - const: fsl,qe-ucc-qmc-hdlc

          - const: fsl,qmc-hdlc



      reg:

        minimum: 0

        maximum: 63

        description:

          The channel number



      fsl,operational-mode:

        $ref: /schemas/types.yaml#/definitions/string

        enum: [transparent, hdlc]

        default: transparent

        description: |

          The channel operational mode

            - hdlc: The channel handles HDLC frames

            - transparent: The channel handles raw data without any processing



      fsl,reverse-data:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The bit order as seen on the channels is reversed,

          transmitting/receiving the MSB of each octet first.

          This flag is used only in 'transparent' mode.



      fsl,tx-ts-mask:

        $ref: /schemas/types.yaml#/definitions/uint64

        description:

          Channel assigned Tx time-slots within the Tx time-slots routed by the

          TSA to this cell.



      fsl,rx-ts-mask:

        $ref: /schemas/types.yaml#/definitions/uint64

        description:

          Channel assigned Rx time-slots within the Rx time-slots routed by the

          TSA to this cell.



      fsl,framer:

        $ref: /schemas/types.yaml#/definitions/phandle

        description:

          phandle to the framer node. The framer is in charge of an E1/T1 line

          interface connected to the TDM bus. It can be used to get the E1/T1 line

          status such as link up/down.



    allOf:

      - if:

          properties:

            compatible:

              not:

                contains:

                  const: fsl,qmc-hdlc

        then:

          properties:

            fsl,framer: false



    required:

      - reg

      - fsl,tx-ts-mask

      - fsl,rx-ts-mask



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - fsl,tsa-serial

  - '#address-cells'

  - '#size-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/soc/qe-fsl,tsa.h>



    qmc@a60 {

        compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";

        reg = <0x3200 0x200>,

              <0x10000 0x1000>;

        reg-names = "ucc_regs", "dpram";

        interrupts = <35>;

        interrupt-parent = <&qeic>;

        fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";



        #address-cells = <1>;

        #size-cells = <0>;



        fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;



        channel@16 {

            /* Ch16 : First 4 even TS from all routed from TSA */

            reg = <16>;

            fsl,operational-mode = "transparent";

            fsl,reverse-data;

            fsl,tx-ts-mask = <0x00000000 0x000000aa>;

            fsl,rx-ts-mask = <0x00000000 0x000000aa>;

        };



        channel@17 {

            /* Ch17 : First 4 odd TS from all routed from TSA */

            reg = <17>;

            fsl,operational-mode = "transparent";

            fsl,reverse-data;

            fsl,tx-ts-mask = <0x00000000 0x00000055>;

            fsl,rx-ts-mask = <0x00000000 0x00000055>;

        };



        channel@19 {

            /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */

            compatible = "fsl,mpc8321-ucc-qmc-hdlc",

                         "fsl,qe-ucc-qmc-hdlc",

                         "fsl,qmc-hdlc";

            reg = <19>;

            fsl,operational-mode = "hdlc";

            fsl,tx-ts-mask = <0x00000000 0x0000ff00>;

            fsl,rx-ts-mask = <0x00000000 0x0000ff00>;

            fsl,framer = <&framer>;

        };

    };

MAINTAINERS

+3 −0
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@@ -8996,6 +8996,7 @@ M: Herve Codina <herve.codina@bootlin.com> 
L:	linuxppc-dev@lists.ozlabs.org

S:	Maintained

F:	Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml

F:	Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml

F:	drivers/soc/fsl/qe/qmc.c

F:	include/soc/fsl/qe/qmc.h








@@ -9011,9 +9012,11 @@ M:	Herve Codina <herve.codina@bootlin.com>







L:	linuxppc-dev@lists.ozlabs.org









S:	Maintained









F:	Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml









F:	Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml









F:	drivers/soc/fsl/qe/tsa.c









F:	drivers/soc/fsl/qe/tsa.h









F:	include/dt-bindings/soc/cpm1-fsl,tsa.h









F:	include/dt-bindings/soc/qe-fsl,tsa.h

















FREESCALE QUICC ENGINE UCC ETHERNET DRIVER









L:	netdev@vger.kernel.org
































drivers/soc/fsl/qbman/qman_ccsr.c



+0
−2






























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Diff line number
Diff line







@@ -791,8 +791,6 @@ static int fsl_qman_probe(struct platform_device *pdev)







	 * FQD memory MUST be zero'd by software









	 */









	zero_priv_mem(fqd_a, fqd_sz);









#else









	WARN(1, "Unexpected architecture using non shared-dma-mem reservations");









#endif









	dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);










































drivers/soc/fsl/qbman/qman_portal.c



+3
−2






























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Diff line number
Diff line







@@ -48,9 +48,10 @@ static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu)







	struct device *dev = pcfg->dev;









	int ret;



















	pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type);









	if (!pcfg->iommu_domain) {









	pcfg->iommu_domain = iommu_paging_domain_alloc(dev);









	if (IS_ERR(pcfg->iommu_domain)) {









		dev_err(dev, "%s(): iommu_domain_alloc() failed", __func__);









		pcfg->iommu_domain = NULL;









		goto no_iommu;









	}









	ret = fsl_pamu_configure_l1_stash(pcfg->iommu_domain, cpu);