Loading arch/mips/mips-boards/atlas/atlas_int.c +1 −0 Original line number Diff line number Diff line Loading @@ -245,6 +245,7 @@ void __init arch_init_irq(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) Loading arch/mips/mips-boards/generic/init.c +1 −0 Original line number Diff line number Diff line Loading @@ -294,6 +294,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; Loading include/asm-mips/mips-boards/generic.h +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 #define MIPS_REVISION_CORID_CORE_FPGA4 11 /**** Artificial corid defines ****/ /* Loading Loading
arch/mips/mips-boards/atlas/atlas_int.c +1 −0 Original line number Diff line number Diff line Loading @@ -245,6 +245,7 @@ void __init arch_init_irq(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) Loading
arch/mips/mips-boards/generic/init.c +1 −0 Original line number Diff line number Diff line Loading @@ -294,6 +294,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; Loading
include/asm-mips/mips-boards/generic.h +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 #define MIPS_REVISION_CORID_CORE_FPGA4 11 /**** Artificial corid defines ****/ /* Loading