Commit a1476c2a authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/dp: Consider output_format while computing dsc bpp



While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.

For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.

v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-2-ankit.k.nautiyal@intel.com
parent 4ebf43d0
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+17 −2
Original line number Diff line number Diff line
@@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
				u32 link_clock, u32 lane_count,
				u32 mode_clock, u32 mode_hdisplay,
				bool bigjoiner,
				enum intel_output_format output_format,
				u32 pipe_bpp,
				u32 timeslots)
{
@@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
	bits_per_pixel = ((link_clock * lane_count) * timeslots) /
			 (intel_dp_mode_to_fec_clock(mode_clock) * 8);

	/* Bandwidth required for 420 is half, that of 444 format */
	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
		bits_per_pixel *= 2;

	drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
				"total bw %u pixel clock %u\n",
				bits_per_pixel, timeslots,
@@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,

	if (HAS_DSC(dev_priv) &&
	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
		enum intel_output_format sink_format, output_format;
		int pipe_bpp;

		sink_format = intel_dp_sink_format(connector, mode);
		output_format = intel_dp_output_format(connector, sink_format);
		/*
		 * TBD pass the connector BPC,
		 * for now U8_MAX so that max BPC on that platform would be picked
		 */
		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);

		/*
		 * Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
							    target_clock,
							    mode->hdisplay,
							    bigjoiner,
							    output_format,
							    pipe_bpp, 64) >> 4;
			dsc_slice_count =
				intel_dp_dsc_get_slice_count(intel_dp,
@@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
							    adjusted_mode->crtc_clock,
							    adjusted_mode->crtc_hdisplay,
							    pipe_config->bigjoiner_pipes,
							    pipe_config->output_format,
							    pipe_bpp,
							    timeslots);
			/*
@@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
		 * calculation procedure is bit different for MST case.
		 */
		if (compute_pipe_bpp) {
			u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
							     pipe_config->pipe_bpp);

			pipe_config->dsc.compressed_bpp = min_t(u16,
								dsc_max_output_bpp >> 4,
								pipe_config->pipe_bpp);
								output_bpp);
		}
		pipe_config->dsc.slice_count = dsc_dp_slice_count;
		drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
				u32 link_clock, u32 lane_count,
				u32 mode_clock, u32 mode_hdisplay,
				bool bigjoiner,
				enum intel_output_format output_format,
				u32 pipe_bpp,
				u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+1 −0
Original line number Diff line number Diff line
@@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
							    target_clock,
							    mode->hdisplay,
							    bigjoiner,
							    INTEL_OUTPUT_FORMAT_RGB,
							    pipe_bpp, 64) >> 4;
			dsc_slice_count =
				intel_dp_dsc_get_slice_count(intel_dp,