Commit a14b929b authored by Otto Pflüger's avatar Otto Pflüger Committed by Rob Clark
Browse files

drm/msm/adreno: Add A306A support 



Add support for Adreno 306A GPU what is found in MSM8917 SoC.
This GPU marketing name is Adreno 308.

Signed-off-by: default avatarOtto Pflüger <otto.pflueger@abscue.de>
[use internal name of the GPU, reword the commit message]
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBarnabás Czémán <trabarni@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/605403/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent dbfbb376

drivers/gpu/drm/msm/adreno/a3xx_catalog.c

+11 −0
Original line number Diff line number Diff line
@@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = { 
		.gmem  = SZ_128K,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.chip_ids = ADRENO_CHIP_IDS(0x03000620),

		.family = ADRENO_3XX,

		.revn = 308,

		.fw = {

			[ADRENO_FW_PM4] = "a300_pm4.fw",

			[ADRENO_FW_PFP] = "a300_pfp.fw",

		},

		.gmem = SZ_128K,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a3xx_gpu_init,

	}, {

		.chip_ids = ADRENO_CHIP_IDS(

			0x03020000,

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+11 −3
Original line number Diff line number Diff line
@@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);

	} else if (adreno_is_a306a(adreno_gpu)) {

		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010);

	} else if (adreno_is_a320(adreno_gpu)) {

		/* Set up 16 deep read/write request queues: */

		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);



	/* Enable Clock gating: */

	if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))

	if (adreno_is_a305b(adreno_gpu) ||

	    adreno_is_a306(adreno_gpu) ||

	    adreno_is_a306a(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);

	else if (adreno_is_a320(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
@@ -334,7 +340,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);



	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||

	if (adreno_is_a305(adreno_gpu) ||

	    adreno_is_a306(adreno_gpu) ||

	    adreno_is_a306a(adreno_gpu) ||

	    adreno_is_a320(adreno_gpu)) {

		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+6 −0
Original line number Diff line number Diff line
@@ -324,6 +324,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu *gpu) 
	return adreno_is_revn(gpu, 307);

}



static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)

{

	/* a306a (marketing name is a308) */

	return adreno_is_revn(gpu, 308);

}



static inline bool adreno_is_a320(const struct adreno_gpu *gpu)

{

	return adreno_is_revn(gpu, 320);