Commit a1d63493 authored by Petr Hodina's avatar Petr Hodina Committed by Bjorn Andersson
Browse files

clk: qcom: dispcc-sdm845: Enable parents for pixel clocks 



Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent
clocks are enabled during clock operations, preventing potential
stability issues during display configuration.

Fixes: 81351776 ("clk: qcom: Add display clock controller driver for SDM845")
Signed-off-by: default avatarPetr Hodina <petr.hodina@protonmail.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarDavid Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20260107-stability-discussion-v2-1-ef7717b435ff@protonmail.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent d8300e6e

drivers/clk/qcom/dispcc-sdm845.c

+2 −2
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 
		.name = "disp_cc_mdss_pclk0_clk_src",

		.parent_data = disp_cc_parent_data_4,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),

		.flags = CLK_SET_RATE_PARENT,

		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,

		.ops = &clk_pixel_ops,

	},

};
@@ -295,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 
		.name = "disp_cc_mdss_pclk1_clk_src",

		.parent_data = disp_cc_parent_data_4,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),

		.flags = CLK_SET_RATE_PARENT,

		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,

		.ops = &clk_pixel_ops,

	},

};