Loading arch/sh/kernel/cpu/irq/intc-sh5.c +38 −35 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ void __init plat_irq_setup(void) { unsigned long long __dummy0, __dummy1=~0x00000000100000f0; unsigned long reg; unsigned long data; int i; intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); Loading @@ -196,11 +195,8 @@ void __init plat_irq_setup(void) /* Set default: per-line enable/disable, priority driven ack/eoi */ for (i = 0; i < NR_INTC_IRQS; i++) { if (platform_int_priority[i] != NO_PRIORITY) { for (i = 0; i < NR_INTC_IRQS; i++) irq_desc[i].chip = &intc_irq_type; } } /* Disable all interrupts and set all priorities to 0 to avoid trouble */ Loading @@ -211,13 +207,18 @@ void __init plat_irq_setup(void) ctrl_outl( NO_PRIORITY, reg); #ifdef CONFIG_SH_CAYMAN { unsigned long data; /* Set IRLM */ /* If all the priorities are set to 'no priority', then * assume we are using encoded mode. */ irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \ platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; if (irlm == NO_PRIORITY) { /* IRLM = 0 */ reg = INTC_ICR_CLEAR; Loading @@ -232,7 +233,8 @@ void __init plat_irq_setup(void) /* Set interrupt priorities according to platform description */ for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { /* Upon the 7th, set Priority Register */ ctrl_outl(data, reg); Loading @@ -240,6 +242,7 @@ void __init plat_irq_setup(void) reg += 8; } } #endif /* * And now let interrupts come in. Loading Loading
arch/sh/kernel/cpu/irq/intc-sh5.c +38 −35 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ void __init plat_irq_setup(void) { unsigned long long __dummy0, __dummy1=~0x00000000100000f0; unsigned long reg; unsigned long data; int i; intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); Loading @@ -196,11 +195,8 @@ void __init plat_irq_setup(void) /* Set default: per-line enable/disable, priority driven ack/eoi */ for (i = 0; i < NR_INTC_IRQS; i++) { if (platform_int_priority[i] != NO_PRIORITY) { for (i = 0; i < NR_INTC_IRQS; i++) irq_desc[i].chip = &intc_irq_type; } } /* Disable all interrupts and set all priorities to 0 to avoid trouble */ Loading @@ -211,13 +207,18 @@ void __init plat_irq_setup(void) ctrl_outl( NO_PRIORITY, reg); #ifdef CONFIG_SH_CAYMAN { unsigned long data; /* Set IRLM */ /* If all the priorities are set to 'no priority', then * assume we are using encoded mode. */ irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \ platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; if (irlm == NO_PRIORITY) { /* IRLM = 0 */ reg = INTC_ICR_CLEAR; Loading @@ -232,7 +233,8 @@ void __init plat_irq_setup(void) /* Set interrupt priorities according to platform description */ for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { /* Upon the 7th, set Priority Register */ ctrl_outl(data, reg); Loading @@ -240,6 +242,7 @@ void __init plat_irq_setup(void) reg += 8; } } #endif /* * And now let interrupts come in. Loading