Commit a21b52aa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - Qualcomm QMP driver fixes for missing register offsets and correct N4
   offsets for registers

* tag 'phy-fixes-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsets
  phy: qcom-qmp: pcs: Add missing v6 N4 register offsets
  phy: qcom-qmp: qserdes-txrx: Add missing registers offsets
parents d512d025 163c1a35

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+160 −29
Original line number Diff line number Diff line
@@ -187,6 +187,31 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_TX_TRANSCEIVER_BIAS_EN]	= QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,

};



static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V6_N4_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V6_N4_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]		= QPHY_V6_N4_PCS_PCS_STATUS1,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_N4_PCS_POWER_DOWN_CONTROL,



	/* In PCS_USB */

	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,

	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,



	[QPHY_COM_RESETSM_CNTRL]	= QSERDES_V6_COM_RESETSM_CNTRL,

	[QPHY_COM_C_READY_STATUS]	= QSERDES_V6_COM_C_READY_STATUS,

	[QPHY_COM_CMN_STATUS]		= QSERDES_V6_COM_CMN_STATUS,

	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V6_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V6_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V6_N4_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V6_N4_TX_TX_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]	= QSERDES_V6_N4_TX_TX_EMP_POST1_LVL,

	[QPHY_TX_HIGHZ_DRVR_EN]		= QSERDES_V6_N4_TX_HIGHZ_DRVR_EN,

	[QPHY_TX_TRANSCEIVER_BIAS_EN]	= QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -997,6 +1022,31 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),

};



static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
@@ -1011,6 +1061,19 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1),

};



static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
@@ -1059,6 +1122,74 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02),

};



static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),

};



static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
@@ -1273,20 +1404,20 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 
};



static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),

};



static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
@@ -1794,22 +1925,22 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 
	.pcs_usb_tbl		= x1e80100_usb43dp_pcs_usb_tbl,

	.pcs_usb_tbl_num	= ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),



	.dp_serdes_tbl		= qmp_v6_dp_serdes_tbl,

	.dp_serdes_tbl_num	= ARRAY_SIZE(qmp_v6_dp_serdes_tbl),

	.dp_tx_tbl		= qmp_v6_dp_tx_tbl,

	.dp_tx_tbl_num		= ARRAY_SIZE(qmp_v6_dp_tx_tbl),

	.dp_serdes_tbl		= qmp_v6_n4_dp_serdes_tbl,

	.dp_serdes_tbl_num	= ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl),

	.dp_tx_tbl		= qmp_v6_n4_dp_tx_tbl,

	.dp_tx_tbl_num		= ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl),



	.serdes_tbl_rbr		= qmp_v6_dp_serdes_tbl_rbr,

	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),

	.serdes_tbl_hbr		= qmp_v6_dp_serdes_tbl_hbr,

	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),

	.serdes_tbl_hbr2	= qmp_v6_dp_serdes_tbl_hbr2,

	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),

	.serdes_tbl_hbr3	= qmp_v6_dp_serdes_tbl_hbr3,

	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),

	.serdes_tbl_rbr		= qmp_v6_n4_dp_serdes_tbl_rbr,

	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr),

	.serdes_tbl_hbr		= qmp_v6_n4_dp_serdes_tbl_hbr,

	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr),

	.serdes_tbl_hbr2	= qmp_v6_n4_dp_serdes_tbl_hbr2,

	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2),

	.serdes_tbl_hbr3	= qmp_v6_n4_dp_serdes_tbl_hbr3,

	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3),



	.swing_hbr_rbr		= &qmp_dp_v5_voltage_swing_hbr_rbr,

	.pre_emphasis_hbr_rbr	= &qmp_dp_v5_pre_emphasis_hbr_rbr,

	.swing_hbr_rbr		= &qmp_dp_v6_voltage_swing_hbr_rbr,

	.pre_emphasis_hbr_rbr	= &qmp_dp_v6_pre_emphasis_hbr_rbr,

	.swing_hbr3_hbr2	= &qmp_dp_v5_voltage_swing_hbr3_hbr2,

	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
@@ -1822,7 +1953,7 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 
	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qmp_v45_usb3phy_regs_layout,

	.regs			= qmp_v6_n4_usb3phy_regs_layout,

};



static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef QCOM_PHY_QMP_PCS_V6_N4_H_

#define QCOM_PHY_QMP_PCS_V6_N4_H_



/* Only for QMP V6 N4 PHY - USB/PCIe PCS registers */

#define QPHY_V6_N4_PCS_SW_RESET			0x000

#define QPHY_V6_N4_PCS_PCS_STATUS1		0x014

#define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL	0x040

#define QPHY_V6_N4_PCS_START_CONTROL		0x044

#define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1	0x090

#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1	0x0c4

#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2	0x0c8

#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3	0x0cc

#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6	0x0d8

#define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1	0x0dc

#define QPHY_V6_N4_PCS_RX_SIGDET_LVL		0x188

#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L	0x190

#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H	0x194

#define QPHY_V6_N4_PCS_RATE_SLEW_CNTRL1		0x198

#define QPHY_V6_N4_PCS_RX_CONFIG		0x1b0

#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1	0x1c0

#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2	0x1c4

#define QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG		0x1d0

#define QPHY_V6_N4_PCS_EQ_CONFIG1		0x1dc

#define QPHY_V6_N4_PCS_EQ_CONFIG2		0x1e0

#define QPHY_V6_N4_PCS_EQ_CONFIG5		0x1ec



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h

+13 −0
Original line number Diff line number Diff line
@@ -6,11 +6,24 @@ 
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_



#define QSERDES_V6_N4_TX_CLKBUF_ENABLE			0x08

#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL		0x0c

#define QSERDES_V6_N4_TX_TX_DRV_LVL			0x14

#define QSERDES_V6_N4_TX_RESET_TSYNC_EN			0x1c

#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN		0x20

#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX	0x30

#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX	0x34

#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN		0x48

#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN			0x4c

#define QSERDES_V6_N4_TX_TX_POL_INV			0x50

#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN	0x54

#define QSERDES_V6_N4_TX_LANE_MODE_1			0x78

#define QSERDES_V6_N4_TX_LANE_MODE_2			0x7c

#define QSERDES_V6_N4_TX_LANE_MODE_3			0x80

#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN		0xac

#define QSERDES_V6_N4_TX_TX_BAND			0xd8

#define QSERDES_V6_N4_TX_INTERFACE_SELECT		0xe4

#define QSERDES_V6_N4_TX_VMODE_CTRL1			0xb0



#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2		0x8

#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2		0x18

drivers/phy/qualcomm/phy-qcom-qmp.h

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#include "phy-qcom-qmp-pcs-v6.h"



#include "phy-qcom-qmp-pcs-v6-n4.h"



#include "phy-qcom-qmp-pcs-v6_20.h"



#include "phy-qcom-qmp-pcs-v7.h"