Unverified Commit a2492ff1 authored by Thippeswamy Havalige's avatar Thippeswamy Havalige Committed by Krzysztof Wilczyński
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PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields 

The PCI core already updates the primary, secondary and subordinate bus
number registers fields of the Type 1 header.

Thus, remove the redundant code from the nwl_pcie_bridge_init().

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20231016051102.1180432-2-thippeswamy.havalige@amd.com


Signed-off-by: default avatarThippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
parent 0bb80ecc

drivers/pci/controller/pcie-xilinx-nwl.c

+1 −11
Original line number Diff line number Diff line
@@ -166,7 +166,6 @@ struct nwl_pcie { 
	int irq_intx;

	int irq_misc;

	u32 ecam_value;

	u8 last_busno;

	struct nwl_msi msi;

	struct irq_domain *legacy_irq_domain;

	struct clk *clk;
@@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 
{

	struct device *dev = pcie->dev;

	struct platform_device *pdev = to_platform_device(dev);

	u32 breg_val, ecam_val, first_busno = 0;

	u32 breg_val, ecam_val;

	int err;



	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
@@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 
	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),

			  E_ECAM_BASE_HI);



	/* Get bus range */

	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);

	pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;

	/* Write primary, secondary and subordinate bus numbers */

	ecam_val = first_busno;

	ecam_val |= (first_busno + 1) << 8;

	ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);

	writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));



	if (nwl_pcie_link_up(pcie))

		dev_info(dev, "Link is UP\n");

	else