Commit a2604f8d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'i3c/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux 

Pull i3c updates from Alexandre Belloni:
 "There is not much this this, mostly fixes around interrupt and IBI
  handling:

   - mipi-i3c-hci: interrupt handling fixes

   - svc: i.MX94 and i.MX95 support, IBI handling fixes"

* tag 'i3c/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux:
  i3c: controllers do not need to depend on I3C
  i3c: master: svc: switch to bulk clk API for flexible clock support
  dt-bindings: i3c: silvaco,i3c-master: add i.MX94 and i.MX95 I3C
  i3c: master: svc: skip address resend on repeat START
  i3c: master: svc: Emit STOP asap in the IBI transaction
  i3c: master: svc: Receive IBI requests in interrupt context
  i3c: mipi-i3c-hci: Move unexpected INTR_STATUS print before IO handler
  i3c: mipi-i3c-hci: Change name of INTR_STATUS bit 11
  i3c: mipi-i3c-hci: Clear INTR_STATUS unconditionally
  i3c: mipi-i3c-hci: Fix handling status of i3c_hci_irq_handler()
  i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates
parents 9bebf9f9 00286d7d

Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml

+39 −6
Original line number Diff line number Diff line
@@ -9,14 +9,17 @@ title: Silvaco I3C master 
maintainers:

  - Conor Culhane <conor.culhane@silvaco.com>



allOf:

  - $ref: i3c.yaml#



properties:

  compatible:

    enum:

    oneOf:

      - enum:

          - nuvoton,npcm845-i3c

          - silvaco,i3c-master-v1

      - items:

          - enum:

              - nxp,imx94-i3c

              - nxp,imx95-i3c

          - const: silvaco,i3c-master-v1



  reg:

    maxItems: 1
@@ -25,12 +28,14 @@ properties: 
    maxItems: 1



  clocks:

    minItems: 2

    items:

      - description: system clock

      - description: bus clock

      - description: other (slower) events clock



  clock-names:

    minItems: 2

    items:

      - const: pclk

      - const: fast_clk
@@ -46,6 +51,34 @@ required: 
  - clock-names

  - clocks



allOf:

  - $ref: i3c.yaml#

  - if:

      properties:

        compatible:

          enum:

            - nuvoton,npcm845-i3c

            - silvaco,i3c-master-v1

    then:

      properties:

        clocks:

          minItems: 3

        clock-names:

          minItems: 3

  - if:

      properties:

        compatible:

          contains:

            enum:

              - nxp,imx94-i3c

              - nxp,imx95-i3c

    then:

      properties:

        clocks:

          maxItems: 2

        clock-names:

          maxItems: 2



unevaluatedProperties: false



examples:

drivers/i3c/master/Kconfig

+0 −4
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

config CDNS_I3C_MASTER

	tristate "Cadence I3C master driver"

	depends on I3C

	depends on HAS_IOMEM

	depends on !(ALPHA || PARISC)

	help
@@ -9,7 +8,6 @@ config CDNS_I3C_MASTER 


config DW_I3C_MASTER

	tristate "Synospsys DesignWare I3C master driver"

	depends on I3C

	depends on HAS_IOMEM

	depends on !(ALPHA || PARISC)

	# ALPHA and PARISC needs {read,write}sl()
@@ -38,7 +36,6 @@ config AST2600_I3C_MASTER 


config SVC_I3C_MASTER

	tristate "Silvaco I3C Dual-Role Master driver"

	depends on I3C

	depends on HAS_IOMEM

	depends on !(ALPHA || PARISC)

	help
@@ -46,7 +43,6 @@ config SVC_I3C_MASTER 


config MIPI_I3C_HCI

	tristate "MIPI I3C Host Controller Interface driver (EXPERIMENTAL)"

	depends on I3C

	depends on HAS_IOMEM

	help

	  Support for hardware following the MIPI Aliance's I3C Host Controller

drivers/i3c/master/mipi-i3c-hci/core.c

+19 −13
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ 
#define INTR_SIGNAL_ENABLE		0x28

#define INTR_FORCE			0x2c

#define INTR_HC_CMD_SEQ_UFLOW_STAT	BIT(12)	/* Cmd Sequence Underflow */

#define INTR_HC_RESET_CANCEL		BIT(11)	/* HC Cancelled Reset */

#define INTR_HC_SEQ_CANCEL		BIT(11)	/* HC Cancelled Transaction Sequence */

#define INTR_HC_INTERNAL_ERR		BIT(10)	/* HC Internal Error */



#define DAT_SECTION			0x30	/* Device Address Table */
@@ -590,26 +590,27 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id) 
	u32 val;



	val = reg_read(INTR_STATUS);

	reg_write(INTR_STATUS, val);

	DBG("INTR_STATUS = %#x", val);



	if (val) {

		reg_write(INTR_STATUS, val);

	}

	if (val)

		result = IRQ_HANDLED;



	if (val & INTR_HC_RESET_CANCEL) {

		DBG("cancelled reset");

		val &= ~INTR_HC_RESET_CANCEL;

	if (val & INTR_HC_SEQ_CANCEL) {

		dev_dbg(&hci->master.dev,

			"Host Controller Cancelled Transaction Sequence\n");

		val &= ~INTR_HC_SEQ_CANCEL;

	}

	if (val & INTR_HC_INTERNAL_ERR) {

		dev_err(&hci->master.dev, "Host Controller Internal Error\n");

		val &= ~INTR_HC_INTERNAL_ERR;

	}



	hci->io->irq_handler(hci);



	if (val)

		dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);

	else

		dev_warn_once(&hci->master.dev,

			      "unexpected INTR_STATUS %#x\n", val);



	if (hci->io->irq_handler(hci))

		result = IRQ_HANDLED;



	return result;
@@ -699,9 +700,14 @@ static int i3c_hci_init(struct i3c_hci *hci) 
	if (ret)

		return -ENXIO;



	/* Disable all interrupts and allow all signal updates */

	/* Disable all interrupts */

	reg_write(INTR_SIGNAL_ENABLE, 0x0);

	reg_write(INTR_STATUS_ENABLE, 0xffffffff);

	/*

	 * Only allow bit 31:10 signal updates because

	 * Bit 0:9 are reserved in IP version >= 0.8

	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code

	 */

	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));



	/* Make sure our data ordering fits the host's */

	regval = reg_read(HC_CONTROL);

drivers/i3c/master/svc-i3c-master.c

+40 −69
Original line number Diff line number Diff line
@@ -201,11 +201,10 @@ struct svc_i3c_drvdata { 
 * @addrs: Array containing the dynamic addresses of each attached device

 * @descs: Array of descriptors, one per attached device

 * @hj_work: Hot-join work

 * @ibi_work: IBI work

 * @irq: Main interrupt

 * @pclk: System clock

 * @num_clks: I3C clock number

 * @fclk: Fast clock (bus)

 * @sclk: Slow clock (other events)

 * @clks: I3C clock array

 * @xferqueue: Transfer queue structure

 * @xferqueue.list: List member

 * @xferqueue.cur: Current ongoing transfer
@@ -229,11 +228,10 @@ struct svc_i3c_master { 
	u8 addrs[SVC_I3C_MAX_DEVS];

	struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS];

	struct work_struct hj_work;

	struct work_struct ibi_work;

	int irq;

	struct clk *pclk;

	int num_clks;

	struct clk *fclk;

	struct clk *sclk;

	struct clk_bulk_data *clks;

	struct {

		struct list_head list;

		struct svc_i3c_xfer *cur;
@@ -487,9 +485,8 @@ static int svc_i3c_master_handle_ibi_won(struct svc_i3c_master *master, u32 msta 
	return ret;

}



static void svc_i3c_master_ibi_work(struct work_struct *work)

static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master)

{

	struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work);

	struct svc_i3c_i2c_dev_data *data;

	unsigned int ibitype, ibiaddr;

	struct i3c_dev_desc *dev;
@@ -504,7 +501,7 @@ static void svc_i3c_master_ibi_work(struct work_struct *work) 
	 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if

	 * any irq or schedule happen during transaction.

	 */

	guard(spinlock_irqsave)(&master->xferqueue.lock);

	guard(spinlock)(&master->xferqueue.lock);



	/*

	 * IBIWON may be set before SVC_I3C_MCTRL_REQUEST_AUTO_IBI, causing
@@ -530,7 +527,7 @@ static void svc_i3c_master_ibi_work(struct work_struct *work) 
	if (ret) {

		dev_err(master->dev, "Timeout when polling for IBIWON\n");

		svc_i3c_master_emit_stop(master);

		goto reenable_ibis;

		return;

	}



	status = readl(master->regs + SVC_I3C_MSTATUS);
@@ -574,17 +571,17 @@ static void svc_i3c_master_ibi_work(struct work_struct *work) 


		svc_i3c_master_emit_stop(master);



		goto reenable_ibis;

		return;

	}



	/* Handle the non critical tasks */

	switch (ibitype) {

	case SVC_I3C_MSTATUS_IBITYPE_IBI:

		svc_i3c_master_emit_stop(master);

		if (dev) {

			i3c_master_queue_ibi(dev, master->ibi.tbq_slot);

			master->ibi.tbq_slot = NULL;

		}

		svc_i3c_master_emit_stop(master);

		break;

	case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:

		svc_i3c_master_emit_stop(master);
@@ -597,9 +594,6 @@ static void svc_i3c_master_ibi_work(struct work_struct *work) 
	default:

		break;

	}



reenable_ibis:

	svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);

}



static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
@@ -618,10 +612,12 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) 
	    !SVC_I3C_MSTATUS_STATE_SLVREQ(active))

		return IRQ_HANDLED;



	svc_i3c_master_disable_interrupts(master);



	/* Handle the interrupt in a non atomic context */

	queue_work(master->base.wq, &master->ibi_work);

	/*

	 * The SDA line remains low until the request is processed.

	 * Receive the request in the interrupt context to respond promptly

	 * and restore the bus to idle state.

	 */

	svc_i3c_master_ibi_isr(master);



	return IRQ_HANDLED;

}
@@ -1281,9 +1277,9 @@ static int svc_i3c_master_write(struct svc_i3c_master *master, 
static int svc_i3c_master_xfer(struct svc_i3c_master *master,

			       bool rnw, unsigned int xfer_type, u8 addr,

			       u8 *in, const u8 *out, unsigned int xfer_len,

			       unsigned int *actual_len, bool continued)

			       unsigned int *actual_len, bool continued, bool repeat_start)

{

	int retry = 2;

	int retry = repeat_start ? 1 : 2;

	u32 reg;

	int ret;
@@ -1468,7 +1464,7 @@ static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) 
		ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,

					  cmd->addr, cmd->in, cmd->out,

					  cmd->len, &cmd->actual_len,

					  cmd->continued);

					  cmd->continued, i > 0);

		/* cmd->xfer is NULL if I2C or CCC transfer */

		if (cmd->xfer)

			cmd->xfer->actual_len = cmd->actual_len;
@@ -1875,42 +1871,11 @@ static const struct i3c_master_controller_ops svc_i3c_master_ops = { 
	.set_speed = svc_i3c_master_set_speed,

};



static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)

{

	int ret = 0;



	ret = clk_prepare_enable(master->pclk);

	if (ret)

		return ret;



	ret = clk_prepare_enable(master->fclk);

	if (ret) {

		clk_disable_unprepare(master->pclk);

		return ret;

	}



	ret = clk_prepare_enable(master->sclk);

	if (ret) {

		clk_disable_unprepare(master->pclk);

		clk_disable_unprepare(master->fclk);

		return ret;

	}



	return 0;

}



static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master)

{

	clk_disable_unprepare(master->pclk);

	clk_disable_unprepare(master->fclk);

	clk_disable_unprepare(master->sclk);

}



static int svc_i3c_master_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct svc_i3c_master *master;

	int ret;

	int ret, i;



	master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);

	if (!master)
@@ -1924,30 +1889,33 @@ static int svc_i3c_master_probe(struct platform_device *pdev) 
	if (IS_ERR(master->regs))

		return PTR_ERR(master->regs);



	master->pclk = devm_clk_get(dev, "pclk");

	if (IS_ERR(master->pclk))

		return PTR_ERR(master->pclk);

	master->num_clks = devm_clk_bulk_get_all(dev, &master->clks);

	if (master->num_clks < 0)

		return dev_err_probe(dev, -EINVAL, "can't get I3C clocks\n");



	master->fclk = devm_clk_get(dev, "fast_clk");

	for (i = 0; i < master->num_clks; i++) {

		if (!strcmp(master->clks[i].id, "fast_clk"))

			break;

	}



	if (i == master->num_clks)

		return dev_err_probe(dev, -EINVAL,

				     "can't get I3C peripheral clock\n");



	master->fclk = master->clks[i].clk;

	if (IS_ERR(master->fclk))

		return PTR_ERR(master->fclk);



	master->sclk = devm_clk_get(dev, "slow_clk");

	if (IS_ERR(master->sclk))

		return PTR_ERR(master->sclk);



	master->irq = platform_get_irq(pdev, 0);

	if (master->irq < 0)

		return master->irq;



	master->dev = dev;



	ret = svc_i3c_master_prepare_clks(master);

	ret = clk_bulk_prepare_enable(master->num_clks, master->clks);

	if (ret)

		return ret;

		return dev_err_probe(dev, ret, "can't enable I3C clocks\n");



	INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);

	INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);

	mutex_init(&master->lock);



	ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
@@ -1998,7 +1966,7 @@ static int svc_i3c_master_probe(struct platform_device *pdev) 
	pm_runtime_set_suspended(&pdev->dev);



err_disable_clks:

	svc_i3c_master_unprepare_clks(master);

	clk_bulk_disable_unprepare(master->num_clks, master->clks);



	return ret;

}
@@ -2036,7 +2004,7 @@ static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev) 
	struct svc_i3c_master *master = dev_get_drvdata(dev);



	svc_i3c_save_regs(master);

	svc_i3c_master_unprepare_clks(master);

	clk_bulk_disable_unprepare(master->num_clks, master->clks);

	pinctrl_pm_select_sleep_state(dev);



	return 0;
@@ -2045,9 +2013,12 @@ static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev) 
static int __maybe_unused svc_i3c_runtime_resume(struct device *dev)

{

	struct svc_i3c_master *master = dev_get_drvdata(dev);

	int ret;



	pinctrl_pm_select_default_state(dev);

	svc_i3c_master_prepare_clks(master);

	ret = clk_bulk_prepare_enable(master->num_clks, master->clks);

	if (ret)

		return ret;



	svc_i3c_restore_regs(master);