Commit a2649952 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0 



Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single
CTL is used for both interfaces. As both RM and encoder now handle
active CTLs, drop that feature bit.

Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/641592/
Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-7-5d20655f10ca@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent c1824a79

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

+2 −3
Original line number Diff line number Diff line
@@ -27,17 +27,16 @@ static const struct dpu_mdp_cfg sm8650_mdp = { 
	},

};



/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */

static const struct dpu_ctl_cfg sm8650_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x15000, .len = 0x1000,

		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = CTL_SM8550_MASK,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x16000, .len = 0x1000,

		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = CTL_SM8550_MASK,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+2 −3
Original line number Diff line number Diff line
@@ -37,17 +37,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = { 
	},

};



/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */

static const struct dpu_ctl_cfg sm8150_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+2 −2
Original line number Diff line number Diff line
@@ -41,12 +41,12 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { 
	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

+2 −2
Original line number Diff line number Diff line
@@ -38,12 +38,12 @@ static const struct dpu_ctl_cfg sm7150_ctl[] = { 
	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+2 −3
Original line number Diff line number Diff line
@@ -35,17 +35,16 @@ static const struct dpu_mdp_cfg sm8250_mdp = { 
	},

};



/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */

static const struct dpu_ctl_cfg sm8250_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,