Commit a267d168 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: dump full CP packet header FIFOs 



In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.

Reviewed-by: default avatarPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9f7ce6a9

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+49 −13
Original line number Diff line number Diff line
@@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),

	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),

	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	/* SE status registers */

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)

	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),

	/* packet headers */

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)

};



static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
@@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)

};



enum ta_ras_gfx_subblock {
@@ -7337,6 +7364,11 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer 
			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {

				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);

				for (reg = 0; reg < reg_count; reg++) {

					if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

						drm_printf(p, "%-50s \t 0x%08x\n",

							   "mmCP_MEC_ME2_HEADER_DUMP",

							   adev->gfx.ip_dump_compute_queues[index + reg]);

					else

						drm_printf(p, "%-50s \t 0x%08x\n",

							   gc_cp_reg_list_9[reg].reg_name,

							   adev->gfx.ip_dump_compute_queues[index + reg]);
@@ -7376,6 +7408,10 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block) 
				soc15_grbm_select(adev, 1 + i, j, k, 0, 0);



				for (reg = 0; reg < reg_count; reg++) {

					if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

						adev->gfx.ip_dump_compute_queues[index + reg] =

							RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));

					else

						adev->gfx.ip_dump_compute_queues[index + reg] =

							RREG32(SOC15_REG_ENTRY_OFFSET(

								       gc_cp_reg_list_9[reg]));