Commit a28a0f67 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events intel: Update alderlake/alderlake events to v1.23 

Update alderlake and alderlaken events from v1.21 to v1.23 adding the
changes from:
https://github.com/intel/perfmon/commit/8df4db9433a2aab59dbbac1a70281032d1af7734
https://github.com/intel/perfmon/commit/846bd247c6e04acc572ca56c992e9e65852bbe63

The tsx_cycles_per_elision metric is updated from PR:
https://github.com/intel/perfmon/pull/116



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20231026003149.3287633-1-irogers@google.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 1768d3a0

tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json

+1 −1
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ 
    },

    {

        "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.",

        "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)",

        "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",

        "MetricGroup": "transaction",

        "MetricName": "tsx_cycles_per_elision",

        "ScaleUnit": "1cycles / elision"

tools/perf/pmu-events/arch/x86/alderlake/frontend.json

+36 −6
Original line number Diff line number Diff line
@@ -394,31 +394,61 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",

        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CORE",

        "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",

        "CounterMask": "6",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",

        "CounterMask": "1",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",

        "Invert": "1",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",

        "EventCode": "0x9c",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

        "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",

        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",

        "CounterMask": "6",

        "EventCode": "0x9c",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",

        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",

        "CounterMask": "1",

        "EventCode": "0x9c",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

        "Invert": "1",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

tools/perf/pmu-events/arch/x86/alderlake/memory.json

+2 −2
Original line number Diff line number Diff line
@@ -248,7 +248,7 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",
@@ -278,7 +278,7 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

tools/perf/pmu-events/arch/x86/alderlake/pipeline.json

+19 −1
Original line number Diff line number Diff line
@@ -238,6 +238,15 @@ 
        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of near taken branch instructions retired.",

        "EventCode": "0xc4",

        "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0xc0",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Taken branch instructions retired.",

        "EventCode": "0xc4",
@@ -411,6 +420,15 @@ 
        "UMask": "0x7e",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",

        "EventCode": "0xc5",

        "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x80",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",

        "EventCode": "0xc5",
@@ -842,7 +860,7 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",

        "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",

        "EventCode": "0xad",

        "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",

        "MSRIndex": "0x3F7",

tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json

+2 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",

        "Deprecated": "1",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_DAT_REQUESTS.RD",

        "PerPkg": "1",
@@ -33,6 +34,7 @@ 
    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",

        "Deprecated": "1",

        "EventCode": "0x85",

        "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",

        "PerPkg": "1",