Commit a2e83f27 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Extract intel_dbuf_mdclk_min_tracker_update() 



Extract the stuff that writes the dbuf/mbus ratio stuff
into its own function. Will help with correctly sequencing
the operations done during mbus programming.

Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-9-ville.syrjala@linux.intel.com
parent 8d7fc261

drivers/gpu/drm/i915/display/skl_watermark.c

+25 −18
Original line number Diff line number Diff line
@@ -3653,6 +3653,30 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio 
			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));

}



static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	const struct intel_dbuf_state *old_dbuf_state =

		intel_atomic_get_old_dbuf_state(state);

	const struct intel_dbuf_state *new_dbuf_state =

		intel_atomic_get_new_dbuf_state(state);



	if (DISPLAY_VER(i915) >= 20 &&

	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {

		/*

		 * For Xe2LPD and beyond, when there is a change in the ratio

		 * between MDCLK and CDCLK, updates to related registers need to

		 * happen at a specific point in the CDCLK change sequence. In

		 * that case, we defer to the call to

		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.

		 */

		return;

	}



	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,

					    new_dbuf_state->joined_mbus);

}



static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -3683,10 +3707,6 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state) 
static void update_mbus_pre_enable(struct intel_atomic_state *state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	const struct intel_dbuf_state *old_dbuf_state =

		intel_atomic_get_old_dbuf_state(state);

	const struct intel_dbuf_state *new_dbuf_state =

		intel_atomic_get_new_dbuf_state(state);



	if (!HAS_MBUS_JOINING(i915))

		return;
@@ -3697,20 +3717,7 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state) 
	 */

	intel_dbuf_mbus_join_update(state);



	if (DISPLAY_VER(i915) >= 20 &&

	    old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {

		/*

		 * For Xe2LPD and beyond, when there is a change in the ratio

		 * between MDCLK and CDCLK, updates to related registers need to

		 * happen at a specific point in the CDCLK change sequence. In

		 * that case, we defer to the call to

		 * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.

		 */

		return;

	}



	intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,

					    new_dbuf_state->joined_mbus);

	intel_dbuf_mdclk_min_tracker_update(state);

}



void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)