dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm UNIPHY PCIe 28LP PHY

maintainers:

  - Nitheesh Sekar <quic_nsekar@quicinc.com>

  - Varadarajan Narayanan <quic_varada@quicinc.com>

description:

  PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC

properties:

  compatible:

    enum:

      - qcom,ipq5332-uniphy-pcie-phy

  reg:

    maxItems: 1

  clocks:

    items:

      - description: pcie pipe clock

      - description: pcie ahb clock

  resets:

    items:

      - description: phy reset

      - description: ahb reset

      - description: cfg reset

  "#phy-cells":

    const: 0

  "#clock-cells":

    const: 0

  num-lanes:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2]

required:

  - compatible

  - reg

  - clocks

  - resets

  - "#phy-cells"

  - "#clock-cells"

  - num-lanes

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>

    pcie0_phy: phy@4b0000 {

        compatible = "qcom,ipq5332-uniphy-pcie-phy";

        reg = <0x004b0000 0x800>;

        clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,

                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;

        resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,

                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,

                 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;

        #clock-cells = <0>;

        #phy-cells = <0>;

        num-lanes = <1>;

    };