Commit a2f4ba53 authored by Sandipan Das's avatar Sandipan Das Committed by Sean Christopherson
Browse files

KVM: x86/pmu: Always stuff GuestOnly=1,HostOnly=0 for mediated PMCs on AMD 



On AMD platforms, there is no way to restore PerfCntrGlobalCtl at
VM-Entry or clear it at VM-Exit. Since the register states will be
restored before entering and saved after exiting guest context, the
counters can keep ticking and even overflow leading to chaos while
still in host context.

To avoid this, intecept event selectors, which is already done by mediated
PMU. In addition, always set the GuestOnly bit and clear the HostOnly bit
for PMU selectors on AMD. Doing so allows the counters run only in guest
context even if their enable bits are still set after VM exit and before
host/guest PMU context switch.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarMingwei Zhang <mizhang@google.com>
[sean: massage shortlog]
Tested-by: default avatarXudong Hao <xudong.hao@intel.com>
Tested-by: default avatarManali Shukla <manali.shukla@amd.com>
Link: https://patch.msgid.link/20251206001720.468579-27-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 3db871fe

arch/x86/kvm/svm/pmu.c

+2 −1
Original line number Diff line number Diff line
@@ -166,7 +166,8 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		data &= ~pmu->reserved_bits;

		if (data != pmc->eventsel) {

			pmc->eventsel = data;

			pmc->eventsel_hw = data;

			pmc->eventsel_hw = (data & ~AMD64_EVENTSEL_HOSTONLY) |

					   AMD64_EVENTSEL_GUESTONLY;

			kvm_pmu_request_counter_reprogram(pmc);

		}

		return 0;