Commit a39dd252 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Paolo Abeni
Browse files

ice: Rename E822 to E82X 



When code is applicable for both E822 and E823 devices, rename it from
E822 to E82X.
ICE_PHY_PER_NAC_E822 was unused, so just remove it.

Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 712e8763

drivers/net/ethernet/intel/ice/ice_ptp.c

+24 −24
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 


#define E810_OUT_PROP_DELAY_NS 1



#define UNKNOWN_INCVAL_E822 0x100000000ULL

#define UNKNOWN_INCVAL_E82X 0x100000000ULL



static const struct ptp_pin_desc ice_pin_desc_e810t[] = {

	/* name    idx   func         chan */
@@ -877,7 +877,7 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx) 
}



/**

 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps

 * ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps

 * @pf: Board private structure

 * @tx: the Tx tracking structure to initialize

 * @port: the port this structure tracks
@@ -888,11 +888,11 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx) 
 * registers into chunks based on the port number.

 */

static int

ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)

ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)

{

	tx->block = port / ICE_PORTS_PER_QUAD;

	tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E822;

	tx->len = INDEX_PER_PORT_E822;

	tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;

	tx->len = INDEX_PER_PORT_E82X;

	tx->verify_cached = 0;



	return ice_ptp_alloc_tx_tracker(tx);
@@ -1095,10 +1095,10 @@ static u64 ice_base_incval(struct ice_pf *pf) 


	if (ice_is_e810(hw))

		incval = ICE_PTP_NOMINAL_INCVAL_E810;

	else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)

		incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));

	else if (ice_e82x_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)

		incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));

	else

		incval = UNKNOWN_INCVAL_E822;

		incval = UNKNOWN_INCVAL_E82X;



	dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",

		incval);
@@ -1127,10 +1127,10 @@ static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port) 


	/* need to read FIFO state */

	if (offs == 0 || offs == 1)

		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,

		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO01_STATUS,

					     &val);

	else

		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,

		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO23_STATUS,

					     &val);



	if (err) {
@@ -1158,7 +1158,7 @@ static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port) 
		dev_dbg(ice_pf_to_dev(pf),

			"Port %d Tx FIFO still not empty; resetting quad %d\n",

			port->port_num, quad);

		ice_ptp_reset_ts_memory_quad_e822(hw, quad);

		ice_ptp_reset_ts_memory_quad_e82x(hw, quad);

		port->tx_fifo_busy_cnt = FIFO_OK;

		return 0;

	}
@@ -1203,8 +1203,8 @@ static void ice_ptp_wait_for_offsets(struct kthread_work *work) 


	tx_err = ice_ptp_check_tx_fifo(port);

	if (!tx_err)

		tx_err = ice_phy_cfg_tx_offset_e822(hw, port->port_num);

	rx_err = ice_phy_cfg_rx_offset_e822(hw, port->port_num);

		tx_err = ice_phy_cfg_tx_offset_e82x(hw, port->port_num);

	rx_err = ice_phy_cfg_rx_offset_e82x(hw, port->port_num);

	if (tx_err || rx_err) {

		/* Tx and/or Rx offset not yet configured, try again later */

		kthread_queue_delayed_work(pf->ptp.kworker,
@@ -1233,7 +1233,7 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port) 


	kthread_cancel_delayed_work_sync(&ptp_port->ov_work);



	err = ice_stop_phy_timer_e822(hw, port, true);

	err = ice_stop_phy_timer_e82x(hw, port, true);

	if (err)

		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",

			port, err);
@@ -1276,7 +1276,7 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port) 
	ptp_port->tx_fifo_busy_cnt = 0;



	/* Start the PHY timer in Vernier mode */

	err = ice_start_phy_timer_e822(hw, port);

	err = ice_start_phy_timer_e82x(hw, port);

	if (err)

		goto out_unlock;
@@ -1325,7 +1325,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup) 
	case ICE_PHY_E810:

		/* Do not reconfigure E810 PHY */

		return;

	case ICE_PHY_E822:

	case ICE_PHY_E82X:

		ice_ptp_port_phy_restart(ptp_port);

		return;

	default:
@@ -1351,7 +1351,7 @@ static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold) 
	ice_ptp_reset_ts_memory(hw);



	for (quad = 0; quad < ICE_MAX_QUAD; quad++) {

		err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,

		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					     &val);

		if (err)

			break;
@@ -1365,7 +1365,7 @@ static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold) 
			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

		}



		err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,

		err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					      val);

		if (err)

			break;
@@ -1603,7 +1603,7 @@ static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan, 
	if (ice_is_e810(hw))

		start_time -= E810_OUT_PROP_DELAY_NS;

	else

		start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));

		start_time -= ice_e82x_pps_delay(ice_e82x_time_ref(hw));



	/* 2. Write TARGET time */

	wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
@@ -1842,7 +1842,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) 
	ice_ptp_enable_all_clkout(pf);



	/* Recalibrate and re-enable timestamp blocks for E822/E823 */

	if (hw->phy_model == ICE_PHY_E822)

	if (hw->phy_model == ICE_PHY_E82X)

		ice_ptp_restart_all_phy(pf);

exit:

	if (err) {
@@ -2574,7 +2574,7 @@ void ice_ptp_reset(struct ice_pf *pf) 
	} else {

		kthread_init_delayed_work(&ptp->port.ov_work,

					  ice_ptp_wait_for_offsets);

		err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,

		err = ice_ptp_init_tx_e82x(pf, &ptp->port.tx,

					   ptp->port.port_num);

	}

	if (err)
@@ -2947,11 +2947,11 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port) 
	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_ptp_init_tx_e810(pf, &ptp_port->tx);

	case ICE_PHY_E822:

	case ICE_PHY_E82X:

		kthread_init_delayed_work(&ptp_port->ov_work,

					  ice_ptp_wait_for_offsets);



		return ice_ptp_init_tx_e822(pf, &ptp_port->tx,

		return ice_ptp_init_tx_e82x(pf, &ptp_port->tx,

					    ptp_port->port_num);

	default:

		return -ENODEV;
@@ -3038,7 +3038,7 @@ static void ice_ptp_remove_auxbus_device(struct ice_pf *pf) 
static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)

{

	switch (pf->hw.phy_model) {

	case ICE_PHY_E822:

	case ICE_PHY_E82X:

		/* E822 based PHY has the clock owner process the interrupt

		 * for all ports.

		 */

drivers/net/ethernet/intel/ice/ice_ptp.h

+1 −1
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ struct ice_ptp_tx { 


/* Quad and port information for initializing timestamp blocks */

#define INDEX_PER_QUAD			64

#define INDEX_PER_PORT_E822		16

#define INDEX_PER_PORT_E82X		16

#define INDEX_PER_PORT_E810		64



/**

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

+6 −6
Original line number Diff line number Diff line
@@ -9,17 +9,17 @@ 
 */

/* Constants defined for the PTP 1588 clock hardware. */



/* struct ice_time_ref_info_e822

/* struct ice_time_ref_info_e82x

 *

 * E822 hardware can use different sources as the reference for the PTP

 * hardware clock. Each clock has different characteristics such as a slightly

 * different frequency, etc.

 *

 * This lookup table defines several constants that depend on the current time

 * reference. See the struct ice_time_ref_info_e822 for information about the

 * reference. See the struct ice_time_ref_info_e82x for information about the

 * meaning of each constant.

 */

const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {

const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {

	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */

	{

		/* pll_freq */
@@ -81,7 +81,7 @@ const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = { 
	},

};



const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {

const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {

	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */

	{

		/* refclk_pre_div */
@@ -155,7 +155,7 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = { 
	},

};



/* struct ice_vernier_info_e822

/* struct ice_vernier_info_e82x

 *

 * E822 hardware calibrates the delay of the timestamp indication from the

 * actual packet transmission or reception during the initialization of the
@@ -168,7 +168,7 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = { 
 * used by this link speed, and that the register should be cleared by writing

 * 0. Other values specify the clock frequency in Hz.

 */

const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {

const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = {

	/* ICE_PTP_LNK_SPD_1G */

	{

		/* tx_par_clk */

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+222 −222

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+24 −24
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ enum ice_ptp_fec_mode { 
};



/**

 * struct ice_time_ref_info_e822

 * struct ice_time_ref_info_e82x

 * @pll_freq: Frequency of PLL that drives timer ticks in Hz

 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L

 * @pps_delay: propagation delay of the PPS output signal
@@ -50,14 +50,14 @@ enum ice_ptp_fec_mode { 
 * Characteristic information for the various TIME_REF sources possible in the

 * E822 devices

 */

struct ice_time_ref_info_e822 {

struct ice_time_ref_info_e82x {

	u64 pll_freq;

	u64 nominal_incval;

	u8 pps_delay;

};



/**

 * struct ice_vernier_info_e822

 * struct ice_vernier_info_e82x

 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS

 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS

 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
@@ -80,7 +80,7 @@ struct ice_time_ref_info_e822 { 
 * different link speeds, either the deskew marker for multi-lane link speeds

 * or the Reed Solomon gearbox marker for RS-FEC.

 */

struct ice_vernier_info_e822 {

struct ice_vernier_info_e82x {

	u32 tx_par_clk;

	u32 rx_par_clk;

	u32 tx_pcs_clk;
@@ -95,7 +95,7 @@ struct ice_vernier_info_e822 { 
};



/**

 * struct ice_cgu_pll_params_e822

 * struct ice_cgu_pll_params_e82x

 * @refclk_pre_div: Reference clock pre-divisor

 * @feedback_div: Feedback divisor

 * @frac_n_div: Fractional divisor
@@ -104,7 +104,7 @@ struct ice_vernier_info_e822 { 
 * Clock Generation Unit parameters used to program the PLL based on the

 * selected TIME_REF frequency.

 */

struct ice_cgu_pll_params_e822 {

struct ice_cgu_pll_params_e82x {

	u32 refclk_pre_div;

	u32 feedback_div;

	u32 frac_n_div;
@@ -124,7 +124,7 @@ enum ice_phy_rclk_pins { 
};



#define ICE_E810_RCLK_PINS_NUM		(ICE_RCLKB_PIN + 1)

#define ICE_E822_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)

#define ICE_E82X_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)

#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \

					  (_pin) + ZL_REF1P)
@@ -183,16 +183,16 @@ struct ice_cgu_pin_desc { 
};



extern const struct

ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];

ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];



#define E810C_QSFP_C827_0_HANDLE 2

#define E810C_QSFP_C827_1_HANDLE 3



/* Table of constants related to possible TIME_REF sources */

extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];

extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];



/* Table of constants for Vernier calibration on E822 */

extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];

extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];



/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for

 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
@@ -215,23 +215,23 @@ int ice_ptp_init_phc(struct ice_hw *hw); 
int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);



/* E822 family functions */

int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);

int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);

void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);

int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);

int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);

void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);



/**

 * ice_e822_time_ref - Get the current TIME_REF from capabilities

 * ice_e82x_time_ref - Get the current TIME_REF from capabilities

 * @hw: pointer to the HW structure

 *

 * Returns the current TIME_REF from the capabilities structure.

 */

static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)

static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)

{

	return hw->func_caps.ts_func_info.time_ref;

}



/**

 * ice_set_e822_time_ref - Set new TIME_REF

 * ice_set_e82x_time_ref - Set new TIME_REF

 * @hw: pointer to the HW structure

 * @time_ref: new TIME_REF to set

 *
@@ -239,31 +239,31 @@ static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw) 
 * change, such as an update to the CGU registers.

 */

static inline void

ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)

ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)

{

	hw->func_caps.ts_func_info.time_ref = time_ref;

}



static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)

static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)

{

	return e822_time_ref[time_ref].pll_freq;

}



static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)

static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)

{

	return e822_time_ref[time_ref].nominal_incval;

}



static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)

static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)

{

	return e822_time_ref[time_ref].pps_delay;

}



/* E822 Vernier calibration functions */

int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);

int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);

int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);

int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);

int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);

int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);

int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);

int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);



/* E810 family functions */

int ice_ptp_init_phy_e810(struct ice_hw *hw);