Commit a3c7ab16 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: export get_power_profile interface for later use



[why]
export dcn401 get_power_profile for later asic.

Reviewed-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarChuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc259117
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@@ -1790,7 +1790,7 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
	}
}

static int dcn401_get_power_profile(const struct dc_state *context)
int dcn401_get_power_profile(const struct dc_state *context)
{
	int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
	int dpm_level = 0;
+1 −0
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@@ -32,6 +32,7 @@ void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info);

unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);

int dcn401_get_power_profile(const struct dc_state *context);
/* Following are definitions for run time init of reg offsets */

/* HUBP */
+1 −0
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@@ -1791,6 +1791,7 @@ static struct resource_funcs dcn42_res_pool_funcs = {
	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
	.prepare_mcache_programming = dcn42_prepare_mcache_programming,
	.build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params,
	.get_power_profile = dcn401_get_power_profile,
	.get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
	.get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size,
	.get_default_tiling_info = dcn10_get_default_tiling_info
+1 −0
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@@ -586,5 +586,6 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc,
							  enum dc_validate_mode validate_mode);

void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
int dcn42_get_power_profile(const struct dc_state *context);

#endif /* _DCN42_RESOURCE_H_ */