Commit a3e510fd authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Convert from DRM_* to dev_* 



Convert from generic DRM_* to dev_* calls to have device context info.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1bec2f27

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+167 −104
Original line number Diff line number Diff line
@@ -1288,14 +1288,14 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) 
 */

static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)

{

	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);

	dev_err(adev->dev, "Invalid callback to read register 0x%04X\n", reg);

	BUG();

	return 0;

}



static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)

{

	DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);

	dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg);

	BUG();

	return 0;

}
@@ -1312,15 +1312,17 @@ static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg 
 */

static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)

{

	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",

		  reg, v);

	dev_err(adev->dev,

		"Invalid callback to write register 0x%04X with 0x%08X\n", reg,

		v);

	BUG();

}



static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)

{

	DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",

		  reg, v);

	dev_err(adev->dev,

		"Invalid callback to write register 0x%llX with 0x%08X\n", reg,

		v);

	BUG();

}
@@ -1336,14 +1338,15 @@ static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, ui 
 */

static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)

{

	DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);

	dev_err(adev->dev, "Invalid callback to read 64 bit register 0x%04X\n",

		reg);

	BUG();

	return 0;

}



static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)

{

	DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);

	dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg);

	BUG();

	return 0;

}
@@ -1360,14 +1363,16 @@ static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t r 
 */

static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)

{

	DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",

	dev_err(adev->dev,

		"Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",

		reg, v);

	BUG();

}



static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)

{

	DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",

	dev_err(adev->dev,

		"Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",

		reg, v);

	BUG();

}
@@ -1386,7 +1391,8 @@ static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, 
static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,

					  uint32_t block, uint32_t reg)

{

	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",

	dev_err(adev->dev,

		"Invalid callback to read register 0x%04X in block 0x%04X\n",

		reg, block);

	BUG();

	return 0;
@@ -1407,7 +1413,8 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, 
				      uint32_t block,

				      uint32_t reg, uint32_t v)

{

	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",

	dev_err(adev->dev,

		"Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",

		reg, block, v);

	BUG();

}
@@ -1694,7 +1701,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) 


	/* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */

	if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))

		DRM_WARN("System can't access extended configuration space, please check!!\n");

		dev_warn(

			adev->dev,

			"System can't access extended configuration space, please check!!\n");



	/* skip if the bios has already enabled large BAR */

	if (adev->gmc.real_vram_size &&
@@ -1734,9 +1743,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) 


	r = pci_resize_resource(adev->pdev, 0, rbar_size);

	if (r == -ENOSPC)

		DRM_INFO("Not enough PCI address space for a large BAR.");

		dev_info(adev->dev,

			 "Not enough PCI address space for a large BAR.");

	else if (r && r != -ENOTSUPP)

		DRM_ERROR("Problem resizing BAR0 (%d).", r);

		dev_err(adev->dev, "Problem resizing BAR0 (%d).", r);



	pci_assign_unassigned_bus_resources(adev->pdev->bus);
@@ -1838,7 +1848,7 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) 
	case 0:

		return false;

	default:

		DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",

		dev_err(adev->dev, "Invalid value for amdgpu.seamless: %d\n",

			amdgpu_seamless);

		return false;

	}
@@ -2015,7 +2025,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) 
		return;



	if (!is_os_64) {

		DRM_WARN("Not 64-bit OS, feature not supported\n");

		dev_warn(adev->dev, "Not 64-bit OS, feature not supported\n");

		goto def_value;

	}

	si_meminfo(&si);
@@ -2030,7 +2040,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) 
		if (total_memory < dram_size_seven_GB)

			goto def_value1;

	} else {

		DRM_WARN("Smu memory pool size not supported\n");

		dev_warn(adev->dev, "Smu memory pool size not supported\n");

		goto def_value;

	}

	adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
@@ -2038,7 +2048,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) 
	return;



def_value1:

	DRM_WARN("No enough system memory\n");

	dev_warn(adev->dev, "No enough system memory\n");

def_value:

	adev->pm.smu_prv_buffer_size = 0;

}
@@ -2202,12 +2212,13 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, 
		amdgpu_device_load_pci_state(pdev);

		r = pci_enable_device(pdev);

		if (r)

			DRM_WARN("pci_enable_device failed (%d)\n", r);

			dev_warn(&pdev->dev, "pci_enable_device failed (%d)\n",

				 r);

		amdgpu_device_resume(dev, true);



		dev->switch_power_state = DRM_SWITCH_POWER_ON;

	} else {

		pr_info("switched off\n");

		dev_info(&pdev->dev, "switched off\n");

		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

		amdgpu_device_prepare(dev);

		amdgpu_device_suspend(dev, true);
@@ -2274,7 +2285,8 @@ int amdgpu_device_ip_set_clockgating_state(void *dev, 
		r = adev->ip_blocks[i].version->funcs->set_clockgating_state(

			&adev->ip_blocks[i], state);

		if (r)

			DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",

			dev_err(adev->dev,

				"set_clockgating_state of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

	}

	return r;
@@ -2308,7 +2320,8 @@ int amdgpu_device_ip_set_powergating_state(void *dev, 
		r = adev->ip_blocks[i].version->funcs->set_powergating_state(

			&adev->ip_blocks[i], state);

		if (r)

			DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",

			dev_err(adev->dev,

				"set_powergating_state of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

	}

	return r;
@@ -2525,7 +2538,9 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) 
			}

		}



		DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",

		dev_info(

			adev->dev,

			"virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",

			amdgpu_virtual_display, pci_address_name,

			adev->enable_virtual_display, adev->mode_info.num_crtc);
@@ -2538,8 +2553,9 @@ void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev) 
	if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {

		adev->mode_info.num_crtc = 1;

		adev->enable_virtual_display = true;

		DRM_INFO("virtual_display:%d, num_crtc:%d\n",

			 adev->enable_virtual_display, adev->mode_info.num_crtc);

		dev_info(adev->dev, "virtual_display:%d, num_crtc:%d\n",

			 adev->enable_virtual_display,

			 adev->mode_info.num_crtc);

	}

}
@@ -2784,16 +2800,18 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
		ip_block = &adev->ip_blocks[i];



		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {

			DRM_WARN("disabled ip block: %d <%s>\n",

				  i, adev->ip_blocks[i].version->funcs->name);

			dev_warn(adev->dev, "disabled ip block: %d <%s>\n", i,

				 adev->ip_blocks[i].version->funcs->name);

			adev->ip_blocks[i].status.valid = false;

		} else if (ip_block->version->funcs->early_init) {

			r = ip_block->version->funcs->early_init(ip_block);

			if (r == -ENOENT) {

				adev->ip_blocks[i].status.valid = false;

			} else if (r) {

				DRM_ERROR("early_init of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"early_init of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				total = false;

			} else {

				adev->ip_blocks[i].status.valid = true;
@@ -2874,8 +2892,10 @@ static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) 
		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {

			r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

			if (r) {

				DRM_ERROR("hw_init of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"hw_init of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				return r;

			}

			adev->ip_blocks[i].status.hw = true;
@@ -2899,7 +2919,8 @@ static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) 
			continue;

		r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

		if (r) {

			DRM_ERROR("hw_init of IP block <%s> failed %d\n",

			dev_err(adev->dev,

				"hw_init of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

			return r;

		}
@@ -2938,8 +2959,11 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) 
			} else {

				r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

				if (r) {

					DRM_ERROR("hw_init of IP block <%s> failed %d\n",

							  adev->ip_blocks[i].version->funcs->name, r);

					dev_err(adev->dev,

						"hw_init of IP block <%s> failed %d\n",

						adev->ip_blocks[i]

							.version->funcs->name,

						r);

					return r;

				}

				adev->ip_blocks[i].status.hw = true;
@@ -2994,19 +3018,22 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) 


		r = drm_sched_init(&ring->sched, &args);

		if (r) {

			DRM_ERROR("Failed to create scheduler on ring %s.\n",

			dev_err(adev->dev,

				"Failed to create scheduler on ring %s.\n",

				ring->name);

			return r;

		}

		r = amdgpu_uvd_entity_init(adev, ring);

		if (r) {

			DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",

			dev_err(adev->dev,

				"Failed to create UVD scheduling entity on ring %s.\n",

				ring->name);

			return r;

		}

		r = amdgpu_vce_entity_init(adev, ring);

		if (r) {

			DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",

			dev_err(adev->dev,

				"Failed to create VCE scheduling entity on ring %s.\n",

				ring->name);

			return r;

		}
@@ -3045,8 +3072,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
		if (adev->ip_blocks[i].version->funcs->sw_init) {

			r = adev->ip_blocks[i].version->funcs->sw_init(&adev->ip_blocks[i]);

			if (r) {

				DRM_ERROR("sw_init of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"sw_init of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				goto init_failed;

			}

		}
@@ -3060,7 +3089,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
			/* need to do common hw init early so everything is set up for gmc */

			r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

			if (r) {

				DRM_ERROR("hw_init %d failed %d\n", i, r);

				dev_err(adev->dev, "hw_init %d failed %d\n", i,

					r);

				goto init_failed;

			}

			adev->ip_blocks[i].status.hw = true;
@@ -3072,17 +3102,21 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 


			r = amdgpu_device_mem_scratch_init(adev);

			if (r) {

				DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);

				dev_err(adev->dev,

					"amdgpu_mem_scratch_init failed %d\n",

					r);

				goto init_failed;

			}

			r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

			if (r) {

				DRM_ERROR("hw_init %d failed %d\n", i, r);

				dev_err(adev->dev, "hw_init %d failed %d\n", i,

					r);

				goto init_failed;

			}

			r = amdgpu_device_wb_init(adev);

			if (r) {

				DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);

				dev_err(adev->dev,

					"amdgpu_device_wb_init failed %d\n", r);

				goto init_failed;

			}

			adev->ip_blocks[i].status.hw = true;
@@ -3094,14 +3128,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
							       AMDGPU_GEM_DOMAIN_GTT,

							       AMDGPU_CSA_SIZE);

				if (r) {

					DRM_ERROR("allocate CSA failed %d\n", r);

					dev_err(adev->dev,

						"allocate CSA failed %d\n", r);

					goto init_failed;

				}

			}



			r = amdgpu_seq64_init(adev);

			if (r) {

				DRM_ERROR("allocate seq64 failed %d\n", r);

				dev_err(adev->dev, "allocate seq64 failed %d\n",

					r);

				goto init_failed;

			}

		}
@@ -3291,8 +3327,10 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 
			r = adev->ip_blocks[i].version->funcs->set_clockgating_state(&adev->ip_blocks[i],

										     state);

			if (r) {

				DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"set_clockgating_state(gate) of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				return r;

			}

		}
@@ -3328,8 +3366,10 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 
			r = adev->ip_blocks[i].version->funcs->set_powergating_state(&adev->ip_blocks[i],

											state);

			if (r) {

				DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"set_powergating_state(gate) of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				return r;

			}

		}
@@ -3395,8 +3435,10 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 
		if (adev->ip_blocks[i].version->funcs->late_init) {

			r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]);

			if (r) {

				DRM_ERROR("late_init of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_err(adev->dev,

					"late_init of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				return r;

			}

		}
@@ -3405,7 +3447,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 


	r = amdgpu_ras_late_init(adev);

	if (r) {

		DRM_ERROR("amdgpu_ras_late_init failed %d", r);

		dev_err(adev->dev, "amdgpu_ras_late_init failed %d", r);

		return r;

	}
@@ -3419,7 +3461,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 


	r = amdgpu_device_enable_mgpu_fan_boost();

	if (r)

		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);

		dev_err(adev->dev, "enable mgpu fan boost failed (%d).\n", r);



	/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */

	if (amdgpu_passthrough(adev) &&
@@ -3452,7 +3494,9 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 
				r = amdgpu_xgmi_set_pstate(gpu_instance->adev,

						AMDGPU_XGMI_PSTATE_MIN);

				if (r) {

					DRM_ERROR("pstate setting failed (%d).\n", r);

					dev_err(adev->dev,

						"pstate setting failed (%d).\n",

						r);

					break;

				}

			}
@@ -3466,16 +3510,18 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 


static void amdgpu_ip_block_hw_fini(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;

	int r;



	if (!ip_block->version->funcs->hw_fini) {

		DRM_ERROR("hw_fini of IP block <%s> not defined\n",

		dev_err(adev->dev, "hw_fini of IP block <%s> not defined\n",

			ip_block->version->funcs->name);

	} else {

		r = ip_block->version->funcs->hw_fini(ip_block);

		/* XXX handle errors */

		if (r) {

			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",

			dev_dbg(adev->dev,

				"hw_fini of IP block <%s> failed %d\n",

				ip_block->version->funcs->name, r);

		}

	}
@@ -3517,7 +3563,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) 


		r = adev->ip_blocks[i].version->funcs->early_fini(&adev->ip_blocks[i]);

		if (r) {

			DRM_DEBUG("early_fini of IP block <%s> failed %d\n",

			dev_dbg(adev->dev,

				"early_fini of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

		}

	}
@@ -3540,7 +3587,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) 


	if (amdgpu_sriov_vf(adev)) {

		if (amdgpu_virt_release_full_gpu(adev, false))

			DRM_ERROR("failed to release exclusive mode on fini\n");

			dev_err(adev->dev,

				"failed to release exclusive mode on fini\n");

	}



	return 0;
@@ -3588,8 +3636,10 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
			r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);

			/* XXX handle errors */

			if (r) {

				DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",

					  adev->ip_blocks[i].version->funcs->name, r);

				dev_dbg(adev->dev,

					"sw_fini of IP block <%s> failed %d\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

			}

		}

		adev->ip_blocks[i].status.sw = false;
@@ -3622,7 +3672,7 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) 


	r = amdgpu_ib_ring_tests(adev);

	if (r)

		DRM_ERROR("ib ring test failed (%d).\n", r);

		dev_err(adev->dev, "ib ring test failed (%d).\n", r);

}



static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
@@ -3763,7 +3813,8 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {

				r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);

				if (r) {

					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",

					dev_err(adev->dev,

						"SMC failed to set mp1 state %d, %d\n",

						adev->mp1_state, r);

					return r;

				}
@@ -4096,7 +4147,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
#else

	default:

		if (amdgpu_dc > 0)

			DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");

			dev_info_once(

				adev->dev,

				"Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");

		return false;

#endif

	}
@@ -4157,7 +4210,8 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) 


fail:

	if (adev->asic_reset_res)

		DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",

		dev_warn(adev->dev,

			 "ASIC reset failed with error, %d for drm dev, %s",

			 adev->asic_reset_res, adev_to_drm(adev)->unique);

	amdgpu_put_xgmi_hive(hive);

}
@@ -4281,7 +4335,7 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) 
		adev->gfx.mcbp = true;



	if (adev->gfx.mcbp)

		DRM_INFO("MCBP is enabled\n");

		dev_info(adev->dev, "MCBP is enabled\n");

}



/**
@@ -4349,7 +4403,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;

	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;



	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",

	dev_info(

		adev->dev,

		"initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",

		amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,

		pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
@@ -4468,8 +4524,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	if (!adev->rmmio)

		return -ENOMEM;



	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);

	DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);

	dev_info(adev->dev, "register mmio base: 0x%08X\n",

		 (uint32_t)adev->rmmio_base);

	dev_info(adev->dev, "register mmio size: %u\n",

		 (unsigned int)adev->rmmio_size);



	/*

	 * Reset domain needs to be present early, before XGMI hive discovered
@@ -4606,7 +4664,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
			r = -EINVAL;

			goto failed;

		}

		DRM_INFO("GPU posting now...\n");

		dev_info(adev->dev, "GPU posting now...\n");

		r = amdgpu_device_asic_init(adev);

		if (r) {

			dev_err(adev->dev, "gpu post error!\n");
@@ -4716,12 +4774,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, 


	r = amdgpu_pm_sysfs_init(adev);

	if (r)

		DRM_ERROR("registering pm sysfs failed (%d).\n", r);

		dev_err(adev->dev, "registering pm sysfs failed (%d).\n", r);



	r = amdgpu_ucode_sysfs_init(adev);

	if (r) {

		adev->ucode_sysfs_en = false;

		DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);

		dev_err(adev->dev, "Creating firmware sysfs failed (%d).\n", r);

	} else

		adev->ucode_sysfs_en = true;
@@ -4970,7 +5028,7 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev) 


	ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);

	if (ret)

		DRM_WARN("evicting device resources failed\n");

		dev_warn(adev->dev, "evicting device resources failed\n");

	return ret;

}
@@ -5093,7 +5151,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) 
	}



	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))

		DRM_WARN("smart shift update failed\n");

		dev_warn(adev->dev, "smart shift update failed\n");



	if (notify_clients)

		drm_client_dev_suspend(adev_to_drm(adev), false);
@@ -5262,7 +5320,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients) 
	adev->in_suspend = false;



	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))

		DRM_WARN("smart shift update failed\n");

		dev_warn(adev->dev, "smart shift update failed\n");



	return 0;

}
@@ -5793,7 +5851,9 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) 
					amdgpu_coredump(tmp_adev, false, vram_lost, reset_context->job);



				if (vram_lost) {

					DRM_INFO("VRAM is lost due to GPU reset!\n");

					dev_info(

						tmp_adev->dev,

						"VRAM is lost due to GPU reset!\n");

					amdgpu_inc_vram_lost(tmp_adev);

				}
@@ -6305,7 +6365,8 @@ static int amdgpu_device_sched_resume(struct list_head *device_list, 
		} else {

			dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));

			if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))

				DRM_WARN("smart shift update failed\n");

				dev_warn(tmp_adev->dev,

					 "smart shift update failed\n");

		}

	}
@@ -6386,7 +6447,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
	 */

	if (need_emergency_restart && amdgpu_ras_get_context(adev) &&

		amdgpu_ras_get_context(adev)->reboot) {

		DRM_WARN("Emergency reboot.");

		dev_warn(adev->dev, "Emergency reboot.");



		ksys_sync_helper();

		emergency_restart();
@@ -7042,11 +7103,11 @@ bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) 
		adev->pci_state = pci_store_saved_state(pdev);



		if (!adev->pci_state) {

			DRM_ERROR("Failed to store PCI saved state");

			dev_err(adev->dev, "Failed to store PCI saved state");

			return false;

		}

	} else {

		DRM_WARN("Failed to save PCI state, err:%d\n", r);

		dev_warn(adev->dev, "Failed to save PCI state, err:%d\n", r);

		return false;

	}
@@ -7067,7 +7128,7 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev) 
	if (!r) {

		pci_restore_state(pdev);

	} else {

		DRM_WARN("Failed to load PCI state, err:%d\n", r);

		dev_warn(adev->dev, "Failed to load PCI state, err:%d\n", r);

		return false;

	}
@@ -7313,7 +7374,7 @@ struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 
	dep = amdgpu_sync_peek_fence(&isolation->prev, ring);

	r = amdgpu_sync_fence(&isolation->active, &f->finished, GFP_NOWAIT);

	if (r)

		DRM_WARN("OOM tracking isolation\n");

		dev_warn(adev->dev, "OOM tracking isolation\n");



out_grab_ref:

	dma_fence_get(dep);
@@ -7381,7 +7442,9 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 
		tmp_ = RREG32(reg_addr);

		loop--;

		if (!loop) {

			DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",

			dev_warn(

				adev->dev,

				"Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",

				inst, reg_name, (uint32_t)expected_value,

				(uint32_t)(tmp_ & (mask)));

			ret = -ETIMEDOUT;

drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

+10 −5
Original line number Diff line number Diff line
@@ -41,7 +41,8 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) 
	if (index < adev->doorbell.num_kernel_doorbells)

		return readl(adev->doorbell.cpu_addr + index);



	DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);

	dev_err(adev->dev, "reading beyond doorbell aperture: 0x%08x!\n",

		index);

	return 0;

}
@@ -63,7 +64,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) 
	if (index < adev->doorbell.num_kernel_doorbells)

		writel(v, adev->doorbell.cpu_addr + index);

	else

		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);

		dev_err(adev->dev,

			"writing beyond doorbell aperture: 0x%08x!\n", index);

}



/**
@@ -83,7 +85,8 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) 
	if (index < adev->doorbell.num_kernel_doorbells)

		return atomic64_read((atomic64_t *)(adev->doorbell.cpu_addr + index));



	DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);

	dev_err(adev->dev, "reading beyond doorbell aperture: 0x%08x!\n",

		index);

	return 0;

}
@@ -105,7 +108,8 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) 
	if (index < adev->doorbell.num_kernel_doorbells)

		atomic64_set((atomic64_t *)(adev->doorbell.cpu_addr + index), v);

	else

		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);

		dev_err(adev->dev,

			"writing beyond doorbell aperture: 0x%08x!\n", index);

}



/**
@@ -166,7 +170,8 @@ int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev) 
				    NULL,

				    (void **)&adev->doorbell.cpu_addr);

	if (r) {

		DRM_ERROR("Failed to allocate kernel doorbells, err=%d\n", r);

		dev_err(adev->dev,

			"Failed to allocate kernel doorbells, err=%d\n", r);

		return r;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+3 −1
Original line number Diff line number Diff line
@@ -295,7 +295,9 @@ static void amdgpu_fence_fallback(struct timer_list *t) 
					      fence_drv.fallback_timer);



	if (amdgpu_fence_process(ring))

		DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);

		dev_warn(ring->adev->dev,

			 "Fence fallback timer expired on ring %s\n",

			 ring->name);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c

+16 −8
Original line number Diff line number Diff line
@@ -144,7 +144,8 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) 


	/* If algo exists, it means that the i2c_adapter's initialized */

	if (!adev->pm.fru_eeprom_i2c_bus || !adev->pm.fru_eeprom_i2c_bus->algo) {

		DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");

		dev_warn(adev->dev,

			 "Cannot access FRU, EEPROM accessor not initialized");

		return -ENODEV;

	}
@@ -152,19 +153,22 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) 
	len = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, fru_addr, buf,

				 sizeof(buf));

	if (len != 8) {

		DRM_ERROR("Couldn't read the IPMI Common Header: %d", len);

		dev_err(adev->dev, "Couldn't read the IPMI Common Header: %d",

			len);

		return len < 0 ? len : -EIO;

	}



	if (buf[0] != 1) {

		DRM_ERROR("Bad IPMI Common Header version: 0x%02x", buf[0]);

		dev_err(adev->dev, "Bad IPMI Common Header version: 0x%02x",

			buf[0]);

		return -EIO;

	}



	for (csum = 0; len > 0; len--)

		csum += buf[len - 1];

	if (csum) {

		DRM_ERROR("Bad IPMI Common Header checksum: 0x%02x", csum);

		dev_err(adev->dev, "Bad IPMI Common Header checksum: 0x%02x",

			csum);

		return -EIO;

	}
@@ -179,12 +183,14 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) 
	/* Read the header of the PIA. */

	len = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addr, buf, 3);

	if (len != 3) {

		DRM_ERROR("Couldn't read the Product Info Area header: %d", len);

		dev_err(adev->dev,

			"Couldn't read the Product Info Area header: %d", len);

		return len < 0 ? len : -EIO;

	}



	if (buf[0] != 1) {

		DRM_ERROR("Bad IPMI Product Info Area version: 0x%02x", buf[0]);

		dev_err(adev->dev, "Bad IPMI Product Info Area version: 0x%02x",

			buf[0]);

		return -EIO;

	}
@@ -197,14 +203,16 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) 
	len = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addr, pia, size);

	if (len != size) {

		kfree(pia);

		DRM_ERROR("Couldn't read the Product Info Area: %d", len);

		dev_err(adev->dev, "Couldn't read the Product Info Area: %d",

			len);

		return len < 0 ? len : -EIO;

	}



	for (csum = 0; size > 0; size--)

		csum += pia[size - 1];

	if (csum) {

		DRM_ERROR("Bad Product Info Area checksum: 0x%02x", csum);

		dev_err(adev->dev, "Bad Product Info Area checksum: 0x%02x",

			csum);

		kfree(pia);

		return -EIO;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+10 −10

File changed.

Preview size limit exceeded, changes collapsed.