Commit a402c663 authored by Varshini Rajendran's avatar Varshini Rajendran Committed by Claudiu Beznea
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clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs 



SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver, a separate
parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
are aligned to the PLL driver by adding the core output freq range in
the PLL characteristics configurations.

Signed-off-by: default avatarVarshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20240729070737.1990756-1-varshini.rajendran@microchip.com


Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 7f1bcdba

drivers/clk/at91/clk-sam9x60-pll.c

+6 −6
Original line number Diff line number Diff line
@@ -23,9 +23,6 @@ 
#define UPLL_DIV		2

#define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)



#define FCORE_MIN		(600000000)

#define FCORE_MAX		(1200000000)



#define PLL_MAX_ID		7



struct sam9x60_pll_core {
@@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, 
	unsigned long nmul = 0;

	unsigned long nfrac = 0;



	if (rate < FCORE_MIN || rate > FCORE_MAX)

	if (rate < core->characteristics->core_output[0].min ||

	    rate > core->characteristics->core_output[0].max)

		return -ERANGE;



	/*
@@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, 
	}



	/* Check if resulted rate is a valid.  */

	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)

	if (tmprate < core->characteristics->core_output[0].min ||

	    tmprate > core->characteristics->core_output[0].max)

		return -ERANGE;



	if (update) {
@@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 
			goto free;

		}



		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,

		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,

							characteristics->core_output[0].min,

							parent_rate, true);

		if (ret < 0) {

			hw = ERR_PTR(ret);

drivers/clk/at91/pmc.h

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ struct clk_pll_characteristics { 
	struct clk_range input;

	int num_output;

	const struct clk_range *output;

	const struct clk_range *core_output;

	u16 *icpll;

	u8 *out;

	u8 upll : 1;

drivers/clk/at91/sam9x60.c

+7 −0
Original line number Diff line number Diff line
@@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = { 
	{ .min = 2343750, .max = 1200000000 },

};



/* Fractional PLL core output range. */

static const struct clk_range core_outputs[] = {

	{ .min = 600000000, .max = 1200000000 },

};



static const struct clk_pll_characteristics plla_characteristics = {

	.input = { .min = 12000000, .max = 48000000 },

	.num_output = ARRAY_SIZE(plla_outputs),

	.output = plla_outputs,

	.core_output = core_outputs,

};



static const struct clk_range upll_outputs[] = {
@@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = { 
	.input = { .min = 12000000, .max = 48000000 },

	.num_output = ARRAY_SIZE(upll_outputs),

	.output = upll_outputs,

	.core_output = core_outputs,

	.upll = true,

};

drivers/clk/at91/sama7g5.c

+7 −0
Original line number Diff line number Diff line
@@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] = { 
	{ .min = 2343750, .max = 1200000000 },

};



/* Fractional PLL core output range. */

static const struct clk_range core_outputs[] = {

	{ .min = 600000000, .max = 1200000000 },

};



/* CPU PLL characteristics. */

static const struct clk_pll_characteristics cpu_pll_characteristics = {

	.input = { .min = 12000000, .max = 50000000 },

	.num_output = ARRAY_SIZE(cpu_pll_outputs),

	.output = cpu_pll_outputs,

	.core_output = core_outputs,

};



/* PLL characteristics. */
@@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_characteristics = { 
	.input = { .min = 12000000, .max = 50000000 },

	.num_output = ARRAY_SIZE(pll_outputs),

	.output = pll_outputs,

	.core_output = core_outputs,

};



/*