Commit a4054250 authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets 



Add some missing v6.20 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-2-dfd1c375ef61@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2226ec07

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h

+4 −0
Original line number Diff line number Diff line
@@ -15,10 +15,13 @@ 


#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2			0x08

#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3			0x0c

#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2			0x18

#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS			0x20

#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3		0x34

#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2				0x9c

#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET			0xa0

#define QSERDES_V6_20_RX_DFE_1					0xac

#define QSERDES_V6_20_RX_DFE_2					0xb0

#define QSERDES_V6_20_RX_DFE_3					0xb4

#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL			0xe8

#define QSERDES_V6_20_RX_GM_CAL					0x10c
@@ -41,5 +44,6 @@ 
#define QSERDES_V6_20_RX_MODE_RATE3_B4				0x220

#define QSERDES_V6_20_RX_MODE_RATE3_B5				0x224

#define QSERDES_V6_20_RX_MODE_RATE3_B6				0x228

#define QSERDES_V6_20_RX_BKUP_CTRL1				0x22c



#endif