Commit a40efd07 authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
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clk: renesas: r8a779a0: Add 3DGE module clock 



Describe the 3DGE module clock needed to operate the PowerVR GPU.

Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251106211604.2766465-5-niklas.soderlund+renesas@ragnatech.se


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f8ea1a27

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {

	DEF_MOD("3dge",		  0,	R8A779A0_CLK_ZG),

	DEF_MOD("isp0",		 16,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp1",		 17,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp2",		 18,	R8A779A0_CLK_S1D1),