Commit a41d94a7 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Setup Retry based thrashing prevention on GFX 12.1 



Enable the new UTCL0 retry-based thrashing prevention on GFX 12.1.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarAlex Sierra <alex.sierra@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 44fc86f2

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

+21 −1
Original line number Diff line number Diff line
@@ -2607,6 +2607,24 @@ static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, 
	WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data);

}



static void gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(struct amdgpu_device *adev,

					 int xcc_id)

{

	uint32_t val;



	/* Set the TCP UTCL0 register to enable atomics */

	val = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

					regTCP_UTCL0_THRASHING_CTRL);

	val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2);

	val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL,

					RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x1);

	val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL,

					RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x1);



	WREG32_SOC15(GC, GET_INST(GC, xcc_id),

					regTCP_UTCL0_THRASHING_CTRL, val);

}



static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev,

					 int xcc_id)

{
@@ -2623,8 +2641,10 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) 
{

	int i;



	for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++)

	for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) {

		gfx_v12_1_xcc_enable_atomics(adev, i);

		gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i);

	}

}



static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block)