Commit a4440832 authored by Serhii Pievniev's avatar Serhii Pievniev Committed by Len Brown
Browse files

tools/power/turbostat: Fix microcode patch level output for AMD/Hygon 



turbostat always used the same logic to read the microcode patch level,
which is correct for Intel but not for AMD/Hygon.
While Intel stores the patch level in the upper 32 bits of MSR, AMD
stores it in the lower 32 bits, which causes turbostat to report the
microcode version as 0x0 on AMD/Hygon.

Fix by shifting right by 32 for non-AMD/Hygon, preserving the existing
behavior for Intel and unknown vendors.

Fixes: 3e404846 ("tools/power turbostat: Add --no-msr option")
Signed-off-by: default avatarSerhii Pievniev <spevnev16@gmail.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 99b38fa3

tools/power/x86/turbostat/turbostat.c

+6 −3
Original line number Diff line number Diff line
@@ -9121,10 +9121,13 @@ void process_cpuid() 
	cpuid_has_hv = ecx_flags & (1 << 31);



	if (!no_msr) {

		if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))

		if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) {

			warnx("get_msr(UCODE)");

		else

		} else {

			ucode_patch_valid = true;

			if (!authentic_amd && !hygon_genuine)

				ucode_patch >>= 32;

		}

	}



	/*
@@ -9138,7 +9141,7 @@ void process_cpuid() 
	if (!quiet) {

		fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d)", family, model, stepping, family, model, stepping);

		if (ucode_patch_valid)

			fprintf(outf, " microcode 0x%x", (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));

			fprintf(outf, " microcode 0x%x", (unsigned int)ucode_patch);

		fputc('\n', outf);



		fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);