Commit a448c40f authored by Gangliang Xie's avatar Gangliang Xie Committed by Alex Deucher
Browse files

drm/amd/pm: check pmfw eeprom feature bit



get and check the pmfw eeprom feature bit to
decide if pmfw eeprom is supported

Signed-off-by: default avatarGangliang Xie <ganglxie@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cd5b28a0
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+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ typedef enum {
/*37*/  FEATURE_DVO                         = 37,
/*38*/  FEATURE_XVMINORPSM_CLKSTOP_DS       = 38,
/*39*/  FEATURE_GLOBAL_DPM                  = 39,
/*40*/  FEATURE_NODE_POWER_MANAGER          = 40,
/*40*/  FEATURE_HROM_EN                     = 40,

/*41*/  NUM_FEATURES                        = 41
} FEATURE_LIST_e;
+2 −1
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@@ -465,7 +465,8 @@ enum smu_clk_type {
       __SMU_DUMMY_MAP(GFX_EDC_XVMIN),				\
       __SMU_DUMMY_MAP(GFX_DIDT_XVMIN),				\
       __SMU_DUMMY_MAP(FAN_ABNORMAL),				\
       __SMU_DUMMY_MAP(PIT),
       __SMU_DUMMY_MAP(PIT),				\
       __SMU_DUMMY_MAP(HROM_EN),

#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
+7 −0
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@@ -82,6 +82,7 @@ const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] =
	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT,			FEATURE_DS_MPIOCLK),
	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT,			FEATURE_DS_MP0CLK),
	SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT,			FEATURE_PIT),
	SMU_13_0_12_FEA_MAP(SMU_FEATURE_HROM_EN_BIT,			FEATURE_HROM_EN),
};

const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = {
@@ -1044,10 +1045,16 @@ static const struct ras_eeprom_smu_funcs smu_v13_0_12_eeprom_smu_funcs = {

static void smu_v13_0_12_ras_smu_feature_flags(struct amdgpu_device *adev, uint64_t *flags)
{
	struct smu_context *smu = adev->powerplay.pp_handle;

	if (!flags)
		return;

	*flags = 0ULL;

	if (smu_v13_0_6_cap_supported(smu, SMU_CAP(RAS_EEPROM)))
		*flags |= RAS_SMU_FEATURE_BIT__RAS_EEPROM;

}

const struct ras_smu_drv smu_v13_0_12_ras_smu_drv = {
+3 −0
Original line number Diff line number Diff line
@@ -3913,6 +3913,9 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras
	if (amdgpu_sriov_vf(smu->adev))
		return -EOPNOTSUPP;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_HROM_EN_BIT))
		smu_v13_0_6_cap_set(smu, SMU_CAP(RAS_EEPROM));

	switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
	case IP_VERSION(13, 0, 12):
		*ras_smu_drv = &smu_v13_0_12_ras_smu_drv;
+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ enum smu_v13_0_6_caps {
	SMU_CAP(PLDM_VERSION),
	SMU_CAP(TEMP_METRICS),
	SMU_CAP(NPM_METRICS),
	SMU_CAP(RAS_EEPROM),
	SMU_CAP(ALL),
};