Commit a49cc71e authored by Wenkai Lin's avatar Wenkai Lin Committed by Herbert Xu
Browse files

crypto: hisilicon/sec2 - fix for aead authsize alignment 



The hardware only supports authentication sizes
that are 4-byte aligned. Therefore, the driver
switches to software computation in this case.

Fixes: 2f072d75 ("crypto: hisilicon - Add aead support on SEC2")
Signed-off-by: default avatarWenkai Lin <linwenkai6@hisilicon.com>
Signed-off-by: default avatarChenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 1b284ffc

drivers/crypto/hisilicon/sec2/sec_crypto.c

+9 −13
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ 
#define SEC_TYPE_MASK		0x0F

#define SEC_DONE_MASK		0x0001

#define SEC_ICV_MASK		0x000E

#define SEC_SQE_LEN_RATE_MASK	0x3



#define SEC_TOTAL_IV_SZ(depth)	(SEC_IV_SIZE * (depth))

#define SEC_SGL_SGE_NR		128
@@ -80,16 +79,16 @@ 
#define SEC_TOTAL_PBUF_SZ(depth)	(PAGE_SIZE * SEC_PBUF_PAGE_NUM(depth) +	\

				SEC_PBUF_LEFT_SZ(depth))



#define SEC_SQE_LEN_RATE	4

#define SEC_SQE_CFLAG		2

#define SEC_SQE_AEAD_FLAG	3

#define SEC_SQE_DONE		0x1

#define SEC_ICV_ERR		0x2

#define MIN_MAC_LEN		4

#define MAC_LEN_MASK		0x1U

#define MAX_INPUT_DATA_LEN	0xFFFE00

#define BITS_MASK		0xFF

#define WORD_MASK		0x3

#define BYTE_BITS		0x8

#define BYTES_TO_WORDS(bcount)	((bcount) >> 2)

#define SEC_XTS_NAME_SZ		0x3

#define IV_CM_CAL_NUM		2

#define IV_CL_MASK		0x7
@@ -1171,7 +1170,7 @@ static int sec_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
		goto bad_key;

	}



	if (ctx->a_ctx.a_key_len & SEC_SQE_LEN_RATE_MASK) {

	if (ctx->a_ctx.a_key_len & WORD_MASK) {

		ret = -EINVAL;

		dev_err(dev, "AUTH key length error!\n");

		goto bad_key;
@@ -1579,11 +1578,10 @@ static void sec_auth_bd_fill_ex(struct sec_auth_ctx *ctx, int dir, 


	sec_sqe->type2.a_key_addr = cpu_to_le64(ctx->a_key_dma);



	sec_sqe->type2.mac_key_alg = cpu_to_le32(authsize / SEC_SQE_LEN_RATE);

	sec_sqe->type2.mac_key_alg = cpu_to_le32(BYTES_TO_WORDS(authsize));



	sec_sqe->type2.mac_key_alg |=

			cpu_to_le32((u32)((ctx->a_key_len) /

			SEC_SQE_LEN_RATE) << SEC_AKEY_OFFSET);

			cpu_to_le32((u32)BYTES_TO_WORDS(ctx->a_key_len) << SEC_AKEY_OFFSET);



	sec_sqe->type2.mac_key_alg |=

			cpu_to_le32((u32)(ctx->a_alg) << SEC_AEAD_ALG_OFFSET);
@@ -1635,12 +1633,10 @@ static void sec_auth_bd_fill_ex_v3(struct sec_auth_ctx *ctx, int dir, 
	sqe3->a_key_addr = cpu_to_le64(ctx->a_key_dma);



	sqe3->auth_mac_key |=

			cpu_to_le32((u32)(authsize /

			SEC_SQE_LEN_RATE) << SEC_MAC_OFFSET_V3);

			cpu_to_le32(BYTES_TO_WORDS(authsize) << SEC_MAC_OFFSET_V3);



	sqe3->auth_mac_key |=

			cpu_to_le32((u32)(ctx->a_key_len /

			SEC_SQE_LEN_RATE) << SEC_AKEY_OFFSET_V3);

			cpu_to_le32((u32)BYTES_TO_WORDS(ctx->a_key_len) << SEC_AKEY_OFFSET_V3);



	sqe3->auth_mac_key |=

			cpu_to_le32((u32)(ctx->a_alg) << SEC_AUTH_ALG_OFFSET_V3);
@@ -2230,8 +2226,8 @@ static int sec_aead_spec_check(struct sec_ctx *ctx, struct sec_req *sreq) 
	struct device *dev = ctx->dev;

	int ret;



	/* Hardware does not handle cases where authsize is less than 4 bytes */

	if (unlikely(sz < MIN_MAC_LEN)) {

	/* Hardware does not handle cases where authsize is not 4 bytes aligned */

	if (c_mode == SEC_CMODE_CBC && (sz & WORD_MASK)) {

		sreq->aead_req.fallback = true;

		return -EINVAL;

	}