Commit a4aa1ceb authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

clk: qcom: tcsrcc-glymur: Update register offsets for clock refs 



Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.

Fixes: 2c1d6ce4 ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarJagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0820c937

drivers/clk/qcom/tcsrcc-glymur.c

+27 −27
Original line number Diff line number Diff line
@@ -28,10 +28,10 @@ enum { 
};



static struct clk_branch tcsr_edp_clkref_en = {

	.halt_reg = 0x1c,

	.halt_reg = 0x60,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x1c,

		.enable_reg = 0x60,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_edp_clkref_en",
@@ -45,10 +45,10 @@ static struct clk_branch tcsr_edp_clkref_en = { 
};



static struct clk_branch tcsr_pcie_1_clkref_en = {

	.halt_reg = 0x4,

	.halt_reg = 0x48,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x4,

		.enable_reg = 0x48,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_pcie_1_clkref_en",
@@ -62,10 +62,10 @@ static struct clk_branch tcsr_pcie_1_clkref_en = { 
};



static struct clk_branch tcsr_pcie_2_clkref_en = {

	.halt_reg = 0x8,

	.halt_reg = 0x4c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x8,

		.enable_reg = 0x4c,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_pcie_2_clkref_en",
@@ -79,10 +79,10 @@ static struct clk_branch tcsr_pcie_2_clkref_en = { 
};



static struct clk_branch tcsr_pcie_3_clkref_en = {

	.halt_reg = 0x10,

	.halt_reg = 0x54,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x10,

		.enable_reg = 0x54,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_pcie_3_clkref_en",
@@ -96,10 +96,10 @@ static struct clk_branch tcsr_pcie_3_clkref_en = { 
};



static struct clk_branch tcsr_pcie_4_clkref_en = {

	.halt_reg = 0x14,

	.halt_reg = 0x58,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x14,

		.enable_reg = 0x58,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_pcie_4_clkref_en",
@@ -113,10 +113,10 @@ static struct clk_branch tcsr_pcie_4_clkref_en = { 
};



static struct clk_branch tcsr_usb2_1_clkref_en = {

	.halt_reg = 0x28,

	.halt_reg = 0x6c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x28,

		.enable_reg = 0x6c,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb2_1_clkref_en",
@@ -130,10 +130,10 @@ static struct clk_branch tcsr_usb2_1_clkref_en = { 
};



static struct clk_branch tcsr_usb2_2_clkref_en = {

	.halt_reg = 0x2c,

	.halt_reg = 0x70,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x2c,

		.enable_reg = 0x70,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb2_2_clkref_en",
@@ -147,10 +147,10 @@ static struct clk_branch tcsr_usb2_2_clkref_en = { 
};



static struct clk_branch tcsr_usb2_3_clkref_en = {

	.halt_reg = 0x30,

	.halt_reg = 0x74,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x30,

		.enable_reg = 0x74,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb2_3_clkref_en",
@@ -164,10 +164,10 @@ static struct clk_branch tcsr_usb2_3_clkref_en = { 
};



static struct clk_branch tcsr_usb2_4_clkref_en = {

	.halt_reg = 0x44,

	.halt_reg = 0x88,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x44,

		.enable_reg = 0x88,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb2_4_clkref_en",
@@ -181,10 +181,10 @@ static struct clk_branch tcsr_usb2_4_clkref_en = { 
};



static struct clk_branch tcsr_usb3_0_clkref_en = {

	.halt_reg = 0x20,

	.halt_reg = 0x64,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x20,

		.enable_reg = 0x64,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb3_0_clkref_en",
@@ -198,10 +198,10 @@ static struct clk_branch tcsr_usb3_0_clkref_en = { 
};



static struct clk_branch tcsr_usb3_1_clkref_en = {

	.halt_reg = 0x24,

	.halt_reg = 0x68,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x24,

		.enable_reg = 0x68,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb3_1_clkref_en",
@@ -215,10 +215,10 @@ static struct clk_branch tcsr_usb3_1_clkref_en = { 
};



static struct clk_branch tcsr_usb4_1_clkref_en = {

	.halt_reg = 0x0,

	.halt_reg = 0x44,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x0,

		.enable_reg = 0x44,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb4_1_clkref_en",
@@ -232,10 +232,10 @@ static struct clk_branch tcsr_usb4_1_clkref_en = { 
};



static struct clk_branch tcsr_usb4_2_clkref_en = {

	.halt_reg = 0x18,

	.halt_reg = 0x5c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x18,

		.enable_reg = 0x5c,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "tcsr_usb4_2_clkref_en",
@@ -268,7 +268,7 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = { 
	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x44,

	.max_register = 0x94,

	.fast_io = true,

};