Commit a50b3e27 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Do the timer interrupt only once on CPU 0 ... 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8b200ce4

arch/mips/sibyte/sb1250/time.c

+9 −8
Original line number Diff line number Diff line
@@ -107,18 +107,19 @@ void sb1250_timer_interrupt(struct pt_regs *regs) 
	____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,

		       IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));



	if (cpu == 0) {

		/*

		 * CPU 0 handles the global timer interrupt job

		 */

	if (cpu == 0) {

		ll_timer_interrupt(irq, regs);

	}



	else {

		/*

	 * every CPU should do profiling and process accouting

		 * other CPUs should just do profiling and process accounting

		 */

		ll_local_timer_interrupt(irq, regs);

	}

}



/*

 * We use our own do_gettimeoffset() instead of the generic one,