Commit a52a3c18 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ntb-6.15' of https://github.com/jonmason/ntb 

Pull ntb fixes from Jon Mason:
 "Bug fixes for NTB Switchtec driver mw negative shift, Intel NTB link
  status db, ntb_perf double unmap (in error case), and MSI 64bit
  arithmetic.

  Also, add new AMD NTB PCI IDs, update AMD NTB maintainer, and pull in
  patch to reduce the stack usage in IDT driver"

* tag 'ntb-6.15' of https://github.com/jonmason/ntb:
  ntb_hw_amd: Add NTB PCI ID for new gen CPU
  ntb: reduce stack usage in idt_scan_mws
  ntb: use 64-bit arithmetic for the MSI doorbell mask
  MAINTAINERS: Update AMD NTB maintainers
  ntb_perf: Delete duplicate dmaengine_unmap_put() call in perf_copy_chunk()
  ntb: intel: Fix using link status DB's
  ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans
parents 4a1d8aba bf8a7ce7

MAINTAINERS

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@@ -17244,7 +17244,6 @@ F: Documentation/core-api/symbol-namespaces.rst 
F:	scripts/nsdeps









NTB AMD DRIVER









M:	Sanjay R Mehta <sanju.mehta@amd.com>









M:	Shyam Sundar S K <Shyam-sundar.S-k@amd.com>









L:	ntb@lists.linux.dev









S:	Supported

























drivers/ntb/hw/amd/ntb_hw_amd.c



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@@ -1318,6 +1318,7 @@ static const struct pci_device_id amd_ntb_pci_tbl[] = {







	{ PCI_VDEVICE(AMD, 0x148b), (kernel_ulong_t)&dev_data[1] },









	{ PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] },









	{ PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] },









	{ PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] },









	{ PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] },









	{ 0, }









};
































drivers/ntb/hw/idt/ntb_hw_idt.c



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−11






























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@@ -1041,7 +1041,7 @@ static inline char *idt_get_mw_name(enum idt_mw_type mw_type)







static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,









				       unsigned char *mw_cnt)









{









	struct idt_mw_cfg mws[IDT_MAX_NR_MWS], *ret_mws;









	struct idt_mw_cfg *mws;









	const struct idt_ntb_bar *bars;









	enum idt_mw_type mw_type;









	unsigned char widx, bidx, en_cnt;








@@ -1049,6 +1049,11 @@ static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,







	int aprt_size;









	u32 data;



















	mws = devm_kcalloc(&ndev->ntb.pdev->dev, IDT_MAX_NR_MWS,









			   sizeof(*mws), GFP_KERNEL);









	if (!mws)









		return ERR_PTR(-ENOMEM);



















	/* Retrieve the array of the BARs registers */









	bars = portdata_tbl[port].bars;


















@@ -1103,16 +1108,7 @@ static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,







		}









	}



















	/* Allocate memory for memory window descriptors */









	ret_mws = devm_kcalloc(&ndev->ntb.pdev->dev, *mw_cnt, sizeof(*ret_mws),









			       GFP_KERNEL);









	if (!ret_mws)









		return ERR_PTR(-ENOMEM);



















	/* Copy the info of detected memory windows */









	memcpy(ret_mws, mws, (*mw_cnt)*sizeof(*ret_mws));



















	return ret_mws;









	return mws;









}



















/*
































drivers/ntb/hw/intel/ntb_hw_gen3.c



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@@ -215,6 +215,9 @@ static int gen3_init_ntb(struct intel_ntb_dev *ndev)







	}



















	ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;









	/* Make sure we are not using DB's used for link status */









	if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)









		ndev->db_valid_mask &= ~ndev->db_link_mask;



















	ndev->reg->db_iowrite(ndev->db_valid_mask,









			      ndev->self_mmio +
































drivers/ntb/hw/mscc/ntb_hw_switchtec.c



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−1






























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@@ -288,7 +288,7 @@ static int switchtec_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx,







	if (size != 0 && xlate_pos < 12)









		return -EINVAL;



















	if (!IS_ALIGNED(addr, BIT_ULL(xlate_pos))) {









	if (xlate_pos >= 0 && !IS_ALIGNED(addr, BIT_ULL(xlate_pos))) {









		/*









		 * In certain circumstances we can get a buffer that is









		 * not aligned to its size. (Most of the time