Unverified Commit a53811fb authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'soc_fsl-6.18-1' of https://github.com/chleroy/linux into soc/drivers 

FSL SOC Changes for 6.18:
- Use for_each_online_cpu() instead of for_each_cpu() in qbman
- Update FSL QUICC ENGINE GPIO driver to a standard platform driver
and stop using legacy-of-mm-gpiochip.h header
- Misc fixes on bus/fsl-mc

* tag 'soc_fsl-6.18-1' of https://github.com/chleroy/linux:
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  bus: fsl-mc: Replace snprintf and sprintf with sysfs_emit in sysfs show functions
  bus: fsl-mc: Check return value of platform_get_resource()

Link: https://lore.kernel.org/r/26615a15-3494-435f-b0c1-861122b4b5e1@csgroup.eu


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0a8c3104 5498f078

arch/powerpc/platforms/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -232,7 +232,6 @@ config QE_GPIO 
	bool "QE GPIO support"

	depends on QUICC_ENGINE

	select GPIOLIB

	select OF_GPIO_MM_GPIOCHIP

	help

	  Say Y here if you're going to use hardware that connects to the

	  QE GPIOs.

drivers/bus/fsl-mc/fsl-mc-bus.c

+6 −3
Original line number Diff line number Diff line
@@ -176,7 +176,7 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, 
{

	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);



	return sprintf(buf, "fsl-mc:v%08Xd%s\n", mc_dev->obj_desc.vendor,

	return sysfs_emit(buf, "fsl-mc:v%08Xd%s\n", mc_dev->obj_desc.vendor,

			mc_dev->obj_desc.type);

}

static DEVICE_ATTR_RO(modalias);
@@ -203,7 +203,7 @@ static ssize_t driver_override_show(struct device *dev, 
{

	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);



	return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override);

	return sysfs_emit(buf, "%s\n", mc_dev->driver_override);

}

static DEVICE_ATTR_RW(driver_override);
@@ -1104,6 +1104,9 @@ static int fsl_mc_bus_probe(struct platform_device *pdev) 
	 * Get physical address of MC portal for the root DPRC:

	 */

	plat_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!plat_res)

		return -EINVAL;



	mc_portal_phys_addr = plat_res->start;

	mc_portal_size = resource_size(plat_res);

	mc_portal_base_phys_addr = mc_portal_phys_addr & ~0x3ffffff;

drivers/soc/fsl/qbman/qman_test_stash.c

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static int on_all_cpus(int (*fn)(void)) 
{

	int cpu;



	for_each_cpu(cpu, cpu_online_mask) {

	for_each_online_cpu(cpu) {

		struct bstrap bstrap = {

			.fn = fn,

			.started = ATOMIC_INIT(0)

drivers/soc/fsl/qe/gpio.c

+75 −64
Original line number Diff line number Diff line
@@ -12,18 +12,19 @@ 
#include <linux/spinlock.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/gpio/legacy-of-mm-gpiochip.h>

#include <linux/gpio/consumer.h>

#include <linux/gpio/driver.h>

#include <linux/slab.h>

#include <linux/export.h>

#include <linux/property.h>

#include <linux/platform_device.h>



#include <soc/fsl/qe/qe.h>



#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))



struct qe_gpio_chip {

	struct of_mm_gpio_chip mm_gc;

	struct gpio_chip gc;

	void __iomem *regs;

	spinlock_t lock;



	/* shadowed data register to clear/set bits safely */
@@ -33,11 +34,9 @@ struct qe_gpio_chip { 
	struct qe_pio_regs saved_regs;

};



static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)

static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)

{

	struct qe_gpio_chip *qe_gc =

		container_of(mm_gc, struct qe_gpio_chip, mm_gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	struct qe_pio_regs __iomem *regs = qe_gc->regs;



	qe_gc->cpdata = ioread32be(&regs->cpdata);

	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
@@ -50,20 +49,19 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) 


static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	struct qe_pio_regs __iomem *regs = qe_gc->regs;

	u32 pin_mask = PIN_MASK(gpio);



	return !!(ioread32be(&regs->cpdata) & pin_mask);

}



static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	struct qe_pio_regs __iomem *regs = qe_gc->regs;

	unsigned long flags;

	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	u32 pin_mask = PIN_MASK(gpio);



	spin_lock_irqsave(&qe_gc->lock, flags);
@@ -82,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 
static int qe_gpio_set_multiple(struct gpio_chip *gc,

				unsigned long *mask, unsigned long *bits)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	struct qe_pio_regs __iomem *regs = qe_gc->regs;

	unsigned long flags;

	int i;
@@ -95,9 +92,9 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, 
			break;

		if (__test_and_clear_bit(i, mask)) {

			if (test_bit(i, bits))

				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));

				qe_gc->cpdata |= PIN_MASK(i);

			else

				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));

				qe_gc->cpdata &= ~PIN_MASK(i);

		}

	}
@@ -110,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, 


static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	unsigned long flags;



	spin_lock_irqsave(&qe_gc->lock, flags);



	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	__par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);



	spin_unlock_irqrestore(&qe_gc->lock, flags);
@@ -125,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 


static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)

{

	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);

	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);

	unsigned long flags;
@@ -133,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 


	spin_lock_irqsave(&qe_gc->lock, flags);



	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	__par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);



	spin_unlock_irqrestore(&qe_gc->lock, flags);
@@ -239,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free); 
void qe_pin_set_dedicated(struct qe_pin *qe_pin)

{

	struct qe_gpio_chip *qe_gc = qe_pin->controller;

	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;

	struct qe_pio_regs __iomem *regs = qe_gc->regs;

	struct qe_pio_regs *sregs = &qe_gc->saved_regs;

	int pin = qe_pin->num;

	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
@@ -268,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) 


	iowrite32be(qe_gc->cpdata, &regs->cpdata);

	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);



	spin_unlock_irqrestore(&qe_gc->lock, flags);

}

EXPORT_SYMBOL(qe_pin_set_dedicated);
@@ -283,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated); 
void qe_pin_set_gpio(struct qe_pin *qe_pin)

{

	struct qe_gpio_chip *qe_gc = qe_pin->controller;

	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;

	struct qe_pio_regs __iomem *regs = qe_gc->regs;

	unsigned long flags;



	spin_lock_irqsave(&qe_gc->lock, flags);
@@ -295,45 +289,62 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) 
}

EXPORT_SYMBOL(qe_pin_set_gpio);



static int __init qe_add_gpiochips(void)

static int qe_gpio_probe(struct platform_device *ofdev)

{

	struct device_node *np;



	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {

		int ret;

	struct device *dev = &ofdev->dev;

	struct device_node *np = dev->of_node;

	struct qe_gpio_chip *qe_gc;

		struct of_mm_gpio_chip *mm_gc;

	struct gpio_chip *gc;



		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);

		if (!qe_gc) {

			ret = -ENOMEM;

			goto err;

		}

	qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);

	if (!qe_gc)

		return -ENOMEM;



	spin_lock_init(&qe_gc->lock);



		mm_gc = &qe_gc->mm_gc;

		gc = &mm_gc->gc;

	gc = &qe_gc->gc;



		mm_gc->save_regs = qe_gpio_save_regs;

	gc->base = -1;

	gc->ngpio = QE_PIO_PINS;

	gc->direction_input = qe_gpio_dir_in;

	gc->direction_output = qe_gpio_dir_out;

	gc->get = qe_gpio_get;

	gc->set = qe_gpio_set;

	gc->set_multiple = qe_gpio_set_multiple;

	gc->parent = dev;

	gc->owner = THIS_MODULE;



	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);

	if (!gc->label)

		return -ENOMEM;



	qe_gc->regs = devm_of_iomap(dev, np, 0, NULL);

	if (IS_ERR(qe_gc->regs))

		return PTR_ERR(qe_gc->regs);



	qe_gpio_save_regs(qe_gc);



		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);

		if (ret)

			goto err;

		continue;

err:

		pr_err("%pOF: registration failed with status %d\n",

		       np, ret);

		kfree(qe_gc);

		/* try others anyway */

	return devm_gpiochip_add_data(dev, gc, qe_gc);

}

	return 0;



static const struct of_device_id qe_gpio_match[] = {

	{

		.compatible = "fsl,mpc8323-qe-pario-bank",

	},

	{},

};

MODULE_DEVICE_TABLE(of, qe_gpio_match);



static struct platform_driver qe_gpio_driver = {

	.probe		= qe_gpio_probe,

	.driver		= {

		.name	= "qe-gpio",

		.of_match_table	= qe_gpio_match,

	},

};



static int __init qe_gpio_init(void)

{

	return platform_driver_register(&qe_gpio_driver);

}

arch_initcall(qe_add_gpiochips);
 
arch_initcall(qe_gpio_init);