Commit a5387fbc authored by Rob Herring (Arm)'s avatar Rob Herring (Arm)
Browse files

dt-bindings: fpga: Convert lattice,ice40-fpga-mgr to DT schema 

Convert the lattice,ice40-fpga-mgr binding to DT schema format. It's a
straight-forward conversion.

Link: https://patch.msgid.link/20251029185503.2124434-1-robh@kernel.org


Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent adf60fda

Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml

0 → 100644
+59 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Lattice iCE40 FPGA Manager



maintainers:

  - Joel Holdsworth <joel@airwebreathe.org.uk>



properties:

  compatible:

    const: lattice,ice40-fpga-mgr



  reg:

    maxItems: 1



  spi-max-frequency:

    minimum: 1000000

    maximum: 25000000



  cdone-gpios:

    maxItems: 1

    description: GPIO input connected to CDONE pin



  reset-gpios:

    maxItems: 1

    description:

      Active-low GPIO output connected to CRESET_B pin. Note that unless the

      GPIO is held low during startup, the FPGA will enter Master SPI mode and

      drive SCK with a clock signal potentially jamming other devices on the bus

      until the firmware is loaded.



required:

  - compatible

  - reg

  - spi-max-frequency

  - cdone-gpios

  - reset-gpios



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>



    spi {

        #address-cells = <1>;

        #size-cells = <0>;



        fpga@0 {

            compatible = "lattice,ice40-fpga-mgr";

            reg = <0>;

            spi-max-frequency = <1000000>;

            cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;

            reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;

        };

    };

Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt

deleted100644 → 0
+0 −21
Original line number Diff line number Diff line 
Lattice iCE40 FPGA Manager



Required properties:

- compatible:		Should contain "lattice,ice40-fpga-mgr"

- reg:			SPI chip select

- spi-max-frequency:	Maximum SPI frequency (>=1000000, <=25000000)

- cdone-gpios:		GPIO input connected to CDONE pin

- reset-gpios:		Active-low GPIO output connected to CRESET_B pin. Note

			that unless the GPIO is held low during startup, the

			FPGA will enter Master SPI mode and drive SCK with a

			clock signal potentially jamming other devices on the

			bus until the firmware is loaded.



Example:

	fpga: fpga@0 {

		compatible = "lattice,ice40-fpga-mgr";

		reg = <0>;

		spi-max-frequency = <1000000>;

		cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;

		reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;

	};