Commit a54ec770 authored by Durai Manickam KR's avatar Durai Manickam KR Committed by Vinod Koul
Browse files

dt-bindings: dma: convert atmel-dma.txt to YAML 



Add a description, required properties, appropriate compatibles and
missing properties like clocks and clock-names which are not defined in
the text binding for all the SoCs that are supported by microchip.
Update the text binding name `atmel-dma.txt` to
`atmel,at91sam9g45-dma.yaml` for the files which reference to
`atmel-dma.txt`. Drop Tudor name from maintainers.

Signed-off-by: default avatarDurai Manickam KR <durai.manickamkr@microchip.com>
Signed-off-by: default avatarCharan Pedumuru <charan.pedumuru@microchip.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250203-test-v4-1-a9ec3eded1c7@microchip.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 1c4c8609

Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Atmel Direct Memory Access Controller (DMA)



maintainers:

  - Ludovic Desroches <ludovic.desroches@microchip.com>



description:

  The Atmel Direct Memory Access Controller (DMAC) transfers data from a source

  peripheral to a destination peripheral over one or more AMBA buses. One channel

  is required for each source/destination pair. In the most basic configuration,

  the DMAC has one master interface and one channel. The master interface reads

  the data from a source and writes it to a destination. Two AMBA transfers are

  required for each DMAC data transfer. This is also known as a dual-access transfer.

  The DMAC is programmed via the APB interface.



properties:

  compatible:

    enum:

      - atmel,at91sam9g45-dma

      - atmel,at91sam9rl-dma



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  "#dma-cells":

    description:

      Must be <2>, used to represent the number of integer cells in the dma

      property of client devices. The two cells in order are

      1. The first cell represents the channel number.

      2. The second cell is 0 for RX and 1 for TX transfers.

    const: 2



  clocks:

    maxItems: 1



  clock-names:

    const: dma_clk



required:

  - compatible

  - reg

  - interrupts

  - "#dma-cells"

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    dma-controller@ffffec00 {

        compatible = "atmel,at91sam9g45-dma";

        reg = <0xffffec00 0x200>;

        interrupts = <21>;

        #dma-cells = <2>;

        clocks = <&pmc 2 20>;

        clock-names = "dma_clk";

    };



...

Documentation/devicetree/bindings/dma/atmel-dma.txt

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* Atmel Direct Memory Access Controller (DMA)



Required properties:

- compatible: Should be "atmel,<chip>-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <2>, used to represent the number of integer cells in

the dmas property of client devices.



Example:



dma0: dma@ffffec00 {

	compatible = "atmel,at91sam9g45-dma";

	reg = <0xffffec00 0x200>;

	interrupts = <21>;

	#dma-cells = <2>;

};



DMA clients connected to the Atmel DMA controller must use the format

described in the dma.txt file, using a three-cell specifier for each channel:

a phandle plus two integer cells.

The three cells in order are:



1. A phandle pointing to the DMA controller.

2. The memory interface (16 most significant bits), the peripheral interface

(16 less significant bits).

3. Parameters for the at91 DMA configuration register which are device

dependent:

  - bit 7-0: peripheral identifier for the hardware handshaking interface. The

  identifier can be different for tx and rx.

  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.



Example:



i2c0@i2c@f8010000 {

	compatible = "atmel,at91sam9x5-i2c";

	reg = <0xf8010000 0x100>;

	interrupts = <9 4 6>;

	dmas = <&dma0 1 7>,

	       <&dma0 1 8>;

	dma-names = "tx", "rx";

};

Documentation/devicetree/bindings/misc/atmel-ssc.txt

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@@ -14,7 +14,7 @@ Required properties: 
Required properties for devices compatible with "atmel,at91sam9g45-ssc":

- dmas: DMA specifier, consisting of a phandle to DMA controller node,

  the memory interface and SSC DMA channel ID (for tx and rx).

  See Documentation/devicetree/bindings/dma/atmel-dma.txt for details.

  See Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml for details.

- dma-names: Must be "tx", "rx".



Optional properties:

MAINTAINERS

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@@ -15347,7 +15347,7 @@ M: Ludovic Desroches <ludovic.desroches@microchip.com> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

L:	dmaengine@vger.kernel.org

S:	Supported

F:	Documentation/devicetree/bindings/dma/atmel-dma.txt

F:	Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml

F:	drivers/dma/at_hdmac.c

F:	drivers/dma/at_xdmac.c

F:	include/dt-bindings/dma/at91.h