Commit a5a6ff3d authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR 

The perf stat errors out with UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL
event.

 $perf stat -e uncore_cha_55/event=0x35,umask=0x10c0008101/ -a -- ls
    event syntax error: '..0x35,umask=0x10c0008101/'
                                      \___ Bad event or PMU

The definition of the CHA umask is config:8-15,32-55, which is 32bit.
However, the umask of the event is bigger than 32bit.
This is an error in the original uncore spec.

Add a new umask_ext5 for the new CHA umask range.

Fixes: 949b1138 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Closes: https://lore.kernel.org/linux-perf-users/alpine.LRH.2.20.2401300733310.11354@Diego/


Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20240708185524.1185505-1-kan.liang@linux.intel.com
parent 2b84def9

arch/x86/events/intel/uncore_snbep.c

+4 −2
Original line number Diff line number Diff line
@@ -462,6 +462,7 @@ 
#define SPR_UBOX_DID				0x3250



/* SPR CHA */

#define SPR_CHA_EVENT_MASK_EXT			0xffffffff

#define SPR_CHA_PMON_CTL_TID_EN			(1 << 16)

#define SPR_CHA_PMON_EVENT_MASK			(SNBEP_PMON_RAW_EVENT_MASK | \

						 SPR_CHA_PMON_CTL_TID_EN)
@@ -478,6 +479,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55"); 
DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57");

DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39");

DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55");

DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63");

DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");

DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");

DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
@@ -5959,7 +5961,7 @@ static struct intel_uncore_ops spr_uncore_chabox_ops = { 


static struct attribute *spr_uncore_cha_formats_attr[] = {

	&format_attr_event.attr,

	&format_attr_umask_ext4.attr,

	&format_attr_umask_ext5.attr,

	&format_attr_tid_en2.attr,

	&format_attr_edge.attr,

	&format_attr_inv.attr,
@@ -5995,7 +5997,7 @@ ATTRIBUTE_GROUPS(uncore_alias); 
static struct intel_uncore_type spr_uncore_chabox = {

	.name			= "cha",

	.event_mask		= SPR_CHA_PMON_EVENT_MASK,

	.event_mask_ext		= SPR_RAW_EVENT_MASK_EXT,

	.event_mask_ext		= SPR_CHA_EVENT_MASK_EXT,

	.num_shared_regs	= 1,

	.constraints		= skx_uncore_chabox_constraints,

	.ops			= &spr_uncore_chabox_ops,