Commit a5c05453 authored by Christian Marangi's avatar Christian Marangi Committed by Thomas Bogendoerfer
Browse files

mips: bmips: rework and cache CBR addr handling 



Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.

This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.

bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
with legacy brcm47xx/brcm63xx and generic BMIPS target.

Acked-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 7c48090a

arch/mips/bcm47xx/prom.c

+3 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include <linux/ssb/ssb_driver_chipcommon.h>

#include <linux/ssb/ssb_regs.h>

#include <linux/smp.h>

#include <asm/bmips.h>

#include <asm/bootinfo.h>

#include <bcm47xx.h>

#include <bcm47xx_board.h>
@@ -110,6 +111,8 @@ static __init void prom_init_mem(void) 


void __init prom_init(void)

{

	/* Cache CBR addr before CPU/DMA setup */

	bmips_cbr_addr = BMIPS_GET_CBR();

	prom_init_mem();

	setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);

}

arch/mips/bcm47xx/setup.c

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include <linux/ssb/ssb.h>

#include <linux/ssb/ssb_embedded.h>

#include <linux/bcma/bcma_soc.h>

#include <asm/bmips.h>

#include <asm/bootinfo.h>

#include <asm/idle.h>

#include <asm/prom.h>
@@ -45,6 +46,9 @@ 
#include <bcm47xx.h>

#include <bcm47xx_board.h>



/* CBR addr doesn't change and we can cache it */

void __iomem *bmips_cbr_addr __read_mostly;



union bcm47xx_bus bcm47xx_bus;

EXPORT_SYMBOL(bcm47xx_bus);

arch/mips/bcm63xx/prom.c

+3 −0
Original line number Diff line number Diff line
@@ -22,6 +22,9 @@ void __init prom_init(void) 
{

	u32 reg, mask;



	/* Cache CBR addr before CPU/DMA setup */

	bmips_cbr_addr = BMIPS_GET_CBR();



	bcm63xx_cpu_init();



	/* stop any running watchdog */

arch/mips/bcm63xx/setup.c

+4 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/memblock.h>

#include <linux/ioport.h>

#include <linux/pm.h>

#include <asm/bmips.h>

#include <asm/bootinfo.h>

#include <asm/time.h>

#include <asm/reboot.h>
@@ -22,6 +23,9 @@ 
#include <bcm63xx_io.h>

#include <bcm63xx_gpio.h>



/* CBR addr doesn't change and we can cache it */

void __iomem *bmips_cbr_addr __read_mostly;



void bcm63xx_machine_halt(void)

{

	pr_info("System halted\n");

arch/mips/bmips/dma.c

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; 


void arch_sync_dma_for_cpu_all(void)

{

	void __iomem *cbr = BMIPS_GET_CBR();

	void __iomem *cbr = bmips_cbr_addr;

	u32 cfg;



	if (boot_cpu_type() != CPU_BMIPS3300 &&