Commit a5ef491e authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/irq: rename de_irq_mask[] to de_pipe_imr_mask[] 



Rename the struct intel_display de_irq_mask[] member to
de_pipe_imr_mask[] to reflect its usage more accurately.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/55bbf17df871331c2c34af748cf9cf812d6a65d7.1758198300.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent cb4242e3

drivers/gpu/drm/i915/display/intel_display_core.h

+5 −1
Original line number Diff line number Diff line
@@ -485,7 +485,11 @@ struct intel_display { 
		 * bitfield.

		 */

		u32 ilk_de_imr_mask;

		u32 de_irq_mask[I915_MAX_PIPES];

		/*

		 * Cached value of BDW+ DE pipe IMR to avoid reads in updating

		 * the bitfield.

		 */

		u32 de_pipe_imr_mask[I915_MAX_PIPES];

		u32 pipestat_irq_mask[I915_MAX_PIPES];

	} irq;

drivers/gpu/drm/i915/display/intel_display_irq.c

+8 −8
Original line number Diff line number Diff line
@@ -215,13 +215,13 @@ static void bdw_update_pipe_irq(struct intel_display *display, 
	if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)))

		return;



	new_val = display->irq.de_irq_mask[pipe];

	new_val = display->irq.de_pipe_imr_mask[pipe];

	new_val &= ~interrupt_mask;

	new_val |= (~enabled_irq_mask & interrupt_mask);



	if (new_val != display->irq.de_irq_mask[pipe]) {

		display->irq.de_irq_mask[pipe] = new_val;

		intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]);

	if (new_val != display->irq.de_pipe_imr_mask[pipe]) {

		display->irq.de_pipe_imr_mask[pipe] = new_val;

		intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_pipe_imr_mask[pipe]);

		intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));

	}

}
@@ -2085,8 +2085,8 @@ void gen8_irq_power_well_post_enable(struct intel_display *display, 


	for_each_pipe_masked(display, pipe, pipe_mask)

		intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

					    display->irq.de_irq_mask[pipe],

					    ~display->irq.de_irq_mask[pipe] | extra_ier);

					    display->irq.de_pipe_imr_mask[pipe],

					    ~display->irq.de_pipe_imr_mask[pipe] | extra_ier);



	spin_unlock_irq(&display->irq.lock);

}
@@ -2300,12 +2300,12 @@ void gen8_de_irq_postinstall(struct intel_display *display) 
	}



	for_each_pipe(display, pipe) {

		display->irq.de_irq_mask[pipe] = ~de_pipe_masked;

		display->irq.de_pipe_imr_mask[pipe] = ~de_pipe_masked;



		if (intel_display_power_is_enabled(display,

						   POWER_DOMAIN_PIPE(pipe)))

			intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

						    display->irq.de_irq_mask[pipe],

						    display->irq.de_pipe_imr_mask[pipe],

						    de_pipe_enables);

	}