Commit a5f5e123 authored by Dapeng Mi's avatar Dapeng Mi Committed by Ingo Molnar
Browse files

perf/x86/intel: Don't clear perf metrics overflow bit unconditionally 

The below code would always unconditionally clear other status bits like
perf metrics overflow bit once PEBS buffer overflows:

        status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;

This is incorrect. Perf metrics overflow bit should be cleared only when
fixed counter 3 in PEBS counter group. Otherwise perf metrics overflow
could be missed to handle.

Closes: https://lore.kernel.org/all/20250225110012.GK31462@noisy.programming.kicks-ass.net/


Fixes: 7b2c05a1 ("perf/x86/intel: Generic support for hardware TopDown metrics")
Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20250415104135.318169-1-dapeng1.mi@linux.intel.com
parent 506f981a

arch/x86/events/intel/core.c

+11 −2
Original line number Diff line number Diff line
@@ -3049,7 +3049,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	int bit;

	int handled = 0;

	u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);



	inc_irq_stat(apic_perf_irqs);
@@ -3093,7 +3092,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		handled++;

		x86_pmu_handle_guest_pebs(regs, &data);

		static_call(x86_pmu_drain_pebs)(regs, &data);

		status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;



		/*

		 * PMI throttle may be triggered, which stops the PEBS event.
@@ -3104,6 +3102,15 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		 */

		if (pebs_enabled != cpuc->pebs_enabled)

			wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);



		/*

		 * Above PEBS handler (PEBS counters snapshotting) has updated fixed

		 * counter 3 and perf metrics counts if they are in counter group,

		 * unnecessary to update again.

		 */

		if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&

		    is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))

			status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;

	}



	/*
@@ -3123,6 +3130,8 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		static_call(intel_pmu_update_topdown_event)(NULL, NULL);

	}



	status &= hybrid(cpuc->pmu, intel_ctrl);



	/*

	 * Checkpointed counters can lead to 'spurious' PMIs because the

	 * rollback caused by the PMI will have cleared the overflow status