Commit a6017322 authored by Alexandre Ghiti's avatar Alexandre Ghiti Committed by Paul Walmsley
Browse files

riscv: Move all duplicate insn parsing macros into asm/insn.h 



kernel/traps_misaligned.c and kvm/vcpu_insn.c define the same macros to
extract information from the instructions.

Let's move the definitions into asm/insn.h to avoid this duplication.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20250620-dev-alex-insn_duplicate_v5_manual-v5-3-d865dc9ad180@rivosinc.com


[pjw@kernel.org: updated to apply]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent 833bbb0d

arch/riscv/include/asm/insn.h

+166 −5
Original line number Diff line number Diff line
@@ -286,10 +286,171 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code) 
	       (code & RVC_INSN_J_RS1_MASK) != 0;

}



#define INSN_MATCH_LB		0x3

#define INSN_MASK_LB		0x707f

#define INSN_MATCH_LH		0x1003

#define INSN_MASK_LH		0x707f

#define INSN_MATCH_LW		0x2003

#define INSN_MASK_LW		0x707f

#define INSN_MATCH_LD		0x3003

#define INSN_MASK_LD		0x707f

#define INSN_MATCH_LBU		0x4003

#define INSN_MASK_LBU		0x707f

#define INSN_MATCH_LHU		0x5003

#define INSN_MASK_LHU		0x707f

#define INSN_MATCH_LWU		0x6003

#define INSN_MASK_LWU		0x707f

#define INSN_MATCH_SB		0x23

#define INSN_MASK_SB		0x707f

#define INSN_MATCH_SH		0x1023

#define INSN_MASK_SH		0x707f

#define INSN_MATCH_SW		0x2023

#define INSN_MASK_SW		0x707f

#define INSN_MATCH_SD		0x3023

#define INSN_MASK_SD		0x707f



#define INSN_MATCH_C_LD		0x6000

#define INSN_MASK_C_LD		0xe003

#define INSN_MATCH_C_SD		0xe000

#define INSN_MASK_C_SD		0xe003

#define INSN_MATCH_C_LW		0x4000

#define INSN_MASK_C_LW		0xe003

#define INSN_MATCH_C_SW		0xc000

#define INSN_MASK_C_SW		0xe003

#define INSN_MATCH_C_LDSP	0x6002

#define INSN_MASK_C_LDSP	0xe003

#define INSN_MATCH_C_SDSP	0xe002

#define INSN_MASK_C_SDSP	0xe003

#define INSN_MATCH_C_LWSP	0x4002

#define INSN_MASK_C_LWSP	0xe003

#define INSN_MATCH_C_SWSP	0xc002

#define INSN_MASK_C_SWSP	0xe003



#define INSN_OPCODE_MASK	0x007c

#define INSN_OPCODE_SHIFT	2

#define INSN_OPCODE_SYSTEM	28



#define INSN_MASK_WFI		0xffffffff

#define INSN_MATCH_WFI		0x10500073



#define INSN_MASK_WRS		0xffffffff

#define INSN_MATCH_WRS		0x00d00073



#define INSN_MATCH_CSRRW	0x1073

#define INSN_MASK_CSRRW		0x707f

#define INSN_MATCH_CSRRS	0x2073

#define INSN_MASK_CSRRS		0x707f

#define INSN_MATCH_CSRRC	0x3073

#define INSN_MASK_CSRRC		0x707f

#define INSN_MATCH_CSRRWI	0x5073

#define INSN_MASK_CSRRWI	0x707f

#define INSN_MATCH_CSRRSI	0x6073

#define INSN_MASK_CSRRSI	0x707f

#define INSN_MATCH_CSRRCI	0x7073

#define INSN_MASK_CSRRCI	0x707f



#define INSN_MATCH_FLW		0x2007

#define INSN_MASK_FLW		0x707f

#define INSN_MATCH_FLD		0x3007

#define INSN_MASK_FLD		0x707f

#define INSN_MATCH_FLQ		0x4007

#define INSN_MASK_FLQ		0x707f

#define INSN_MATCH_FSW		0x2027

#define INSN_MASK_FSW		0x707f

#define INSN_MATCH_FSD		0x3027

#define INSN_MASK_FSD		0x707f

#define INSN_MATCH_FSQ		0x4027

#define INSN_MASK_FSQ		0x707f



#define INSN_MATCH_C_FLD	0x2000

#define INSN_MASK_C_FLD		0xe003

#define INSN_MATCH_C_FLW	0x6000

#define INSN_MASK_C_FLW		0xe003

#define INSN_MATCH_C_FSD	0xa000

#define INSN_MASK_C_FSD		0xe003

#define INSN_MATCH_C_FSW	0xe000

#define INSN_MASK_C_FSW		0xe003

#define INSN_MATCH_C_FLDSP	0x2002

#define INSN_MASK_C_FLDSP	0xe003

#define INSN_MATCH_C_FSDSP	0xa002

#define INSN_MASK_C_FSDSP	0xe003

#define INSN_MATCH_C_FLWSP	0x6002

#define INSN_MASK_C_FLWSP	0xe003

#define INSN_MATCH_C_FSWSP	0xe002

#define INSN_MASK_C_FSWSP	0xe003



#define INSN_MATCH_C_LHU		0x8400

#define INSN_MASK_C_LHU			0xfc43

#define INSN_MATCH_C_LH			0x8440

#define INSN_MASK_C_LH			0xfc43

#define INSN_MATCH_C_SH			0x8c00

#define INSN_MASK_C_SH			0xfc43



#define INSN_16BIT_MASK		0x3

#define INSN_IS_16BIT(insn)	(((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)

#define INSN_LEN(insn)		(INSN_IS_16BIT(insn) ? 2 : 4)



#define SHIFT_RIGHT(x, y)		\

	((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))



#define REG_MASK			\

	((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))



#define REG_OFFSET(insn, pos)		\

	(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)



#define REG_PTR(insn, pos, regs)	\

	((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))



#define GET_RS1(insn, regs)	(*REG_PTR(insn, SH_RS1, regs))

#define GET_RS2(insn, regs)	(*REG_PTR(insn, SH_RS2, regs))

#define GET_RS1S(insn, regs)	(*REG_PTR(RVC_RS1S(insn), 0, regs))

#define GET_RS2S(insn, regs)	(*REG_PTR(RVC_RS2S(insn), 0, regs))

#define GET_RS2C(insn, regs)	(*REG_PTR(insn, SH_RS2C, regs))

#define GET_SP(regs)		(*REG_PTR(2, 0, regs))

#define SET_RD(insn, regs, val)	(*REG_PTR(insn, SH_RD, regs) = (val))

#define IMM_I(insn)		((s32)(insn) >> 20)

#define IMM_S(insn)		(((s32)(insn) >> 25 << 5) | \

				 (s32)(((insn) >> 7) & 0x1f))



#define SH_RD			7

#define SH_RS1			15

#define SH_RS2			20

#define SH_RS2C			2

#define MASK_RX			0x1f



#if defined(CONFIG_64BIT)

#define LOG_REGBYTES		3

#else

#define LOG_REGBYTES		2

#endif



#define MASK_FUNCT3		0x7000



#define GET_FUNCT3(insn)	(((insn) >> 12) & 7)



#define RV_IMM_SIGN(x)		(-(((x) >> 31) & 1))

#define RVC_IMM_SIGN(x)		(-(((x) >> 12) & 1))

#define RV_X_MASK(X, s, mask)	(((X) >> (s)) & (mask))

#define RV_X(X, s, n)		RV_X_MASK(X, s, ((1 << (n)) - 1))

#define RVC_LW_IMM(x)		((RV_X(x, 6, 1) << 2) | \

				 (RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 5, 1) << 6))

#define RVC_LD_IMM(x)		((RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 5, 2) << 6))

#define RVC_LWSP_IMM(x)		((RV_X(x, 4, 3) << 2) | \

				 (RV_X(x, 12, 1) << 5) | \

				 (RV_X(x, 2, 2) << 6))

#define RVC_LDSP_IMM(x)		((RV_X(x, 5, 2) << 3) | \

				 (RV_X(x, 12, 1) << 5) | \

				 (RV_X(x, 2, 3) << 6))

#define RVC_SWSP_IMM(x)		((RV_X(x, 9, 4) << 2) | \

				 (RV_X(x, 7, 2) << 6))

#define RVC_SDSP_IMM(x)		((RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 7, 3) << 6))

#define RVC_RS1S(insn)		(8 + RV_X(insn, SH_RD, 3))

#define RVC_RS2S(insn)		(8 + RV_X(insn, SH_RS2C, 3))

#define RVC_RS2(insn)		RV_X(insn, SH_RS2C, 5)

#define RVC_X(X, s, mask)	RV_X_MASK(X, s, mask)



#define RV_EXTRACT_RS1_REG(x) \

arch/riscv/kernel/traps_misaligned.c

+0 −142
Original line number Diff line number Diff line
@@ -20,148 +20,6 @@ 
#include <asm/vector.h>

#include <asm/insn.h>



#define INSN_MATCH_LB			0x3

#define INSN_MASK_LB			0x707f

#define INSN_MATCH_LH			0x1003

#define INSN_MASK_LH			0x707f

#define INSN_MATCH_LW			0x2003

#define INSN_MASK_LW			0x707f

#define INSN_MATCH_LD			0x3003

#define INSN_MASK_LD			0x707f

#define INSN_MATCH_LBU			0x4003

#define INSN_MASK_LBU			0x707f

#define INSN_MATCH_LHU			0x5003

#define INSN_MASK_LHU			0x707f

#define INSN_MATCH_LWU			0x6003

#define INSN_MASK_LWU			0x707f

#define INSN_MATCH_SB			0x23

#define INSN_MASK_SB			0x707f

#define INSN_MATCH_SH			0x1023

#define INSN_MASK_SH			0x707f

#define INSN_MATCH_SW			0x2023

#define INSN_MASK_SW			0x707f

#define INSN_MATCH_SD			0x3023

#define INSN_MASK_SD			0x707f



#define INSN_MATCH_FLW			0x2007

#define INSN_MASK_FLW			0x707f

#define INSN_MATCH_FLD			0x3007

#define INSN_MASK_FLD			0x707f

#define INSN_MATCH_FLQ			0x4007

#define INSN_MASK_FLQ			0x707f

#define INSN_MATCH_FSW			0x2027

#define INSN_MASK_FSW			0x707f

#define INSN_MATCH_FSD			0x3027

#define INSN_MASK_FSD			0x707f

#define INSN_MATCH_FSQ			0x4027

#define INSN_MASK_FSQ			0x707f



#define INSN_MATCH_C_LD			0x6000

#define INSN_MASK_C_LD			0xe003

#define INSN_MATCH_C_SD			0xe000

#define INSN_MASK_C_SD			0xe003

#define INSN_MATCH_C_LW			0x4000

#define INSN_MASK_C_LW			0xe003

#define INSN_MATCH_C_SW			0xc000

#define INSN_MASK_C_SW			0xe003

#define INSN_MATCH_C_LDSP		0x6002

#define INSN_MASK_C_LDSP		0xe003

#define INSN_MATCH_C_SDSP		0xe002

#define INSN_MASK_C_SDSP		0xe003

#define INSN_MATCH_C_LWSP		0x4002

#define INSN_MASK_C_LWSP		0xe003

#define INSN_MATCH_C_SWSP		0xc002

#define INSN_MASK_C_SWSP		0xe003



#define INSN_MATCH_C_FLD		0x2000

#define INSN_MASK_C_FLD			0xe003

#define INSN_MATCH_C_FLW		0x6000

#define INSN_MASK_C_FLW			0xe003

#define INSN_MATCH_C_FSD		0xa000

#define INSN_MASK_C_FSD			0xe003

#define INSN_MATCH_C_FSW		0xe000

#define INSN_MASK_C_FSW			0xe003

#define INSN_MATCH_C_FLDSP		0x2002

#define INSN_MASK_C_FLDSP		0xe003

#define INSN_MATCH_C_FSDSP		0xa002

#define INSN_MASK_C_FSDSP		0xe003

#define INSN_MATCH_C_FLWSP		0x6002

#define INSN_MASK_C_FLWSP		0xe003

#define INSN_MATCH_C_FSWSP		0xe002

#define INSN_MASK_C_FSWSP		0xe003



#define INSN_MATCH_C_LHU		0x8400

#define INSN_MASK_C_LHU			0xfc43

#define INSN_MATCH_C_LH			0x8440

#define INSN_MASK_C_LH			0xfc43

#define INSN_MATCH_C_SH			0x8c00

#define INSN_MASK_C_SH			0xfc43



#define INSN_LEN(insn)			((((insn) & 0x3) < 0x3) ? 2 : 4)



#if defined(CONFIG_64BIT)

#define LOG_REGBYTES			3

#define XLEN				64

#else

#define LOG_REGBYTES			2

#define XLEN				32

#endif

#define REGBYTES			(1 << LOG_REGBYTES)

#define XLEN_MINUS_16			((XLEN) - 16)



#define SH_RD				7

#define SH_RS1				15

#define SH_RS2				20

#define SH_RS2C				2



#define RVC_LW_IMM(x)			((RV_X(x, 6, 1) << 2) | \

					 (RV_X(x, 10, 3) << 3) | \

					 (RV_X(x, 5, 1) << 6))

#define RVC_LD_IMM(x)			((RV_X(x, 10, 3) << 3) | \

					 (RV_X(x, 5, 2) << 6))

#define RVC_LWSP_IMM(x)			((RV_X(x, 4, 3) << 2) | \

					 (RV_X(x, 12, 1) << 5) | \

					 (RV_X(x, 2, 2) << 6))

#define RVC_LDSP_IMM(x)			((RV_X(x, 5, 2) << 3) | \

					 (RV_X(x, 12, 1) << 5) | \

					 (RV_X(x, 2, 3) << 6))

#define RVC_SWSP_IMM(x)			((RV_X(x, 9, 4) << 2) | \

					 (RV_X(x, 7, 2) << 6))

#define RVC_SDSP_IMM(x)			((RV_X(x, 10, 3) << 3) | \

					 (RV_X(x, 7, 3) << 6))

#define RVC_RS1S(insn)			(8 + RV_X(insn, SH_RD, 3))

#define RVC_RS2S(insn)			(8 + RV_X(insn, SH_RS2C, 3))

#define RVC_RS2(insn)			RV_X(insn, SH_RS2C, 5)



#define SHIFT_RIGHT(x, y)		\

	((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))



#define REG_MASK			\

	((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))



#define REG_OFFSET(insn, pos)		\

	(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)



#define REG_PTR(insn, pos, regs)	\

	(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))



#define GET_RS1(insn, regs)		(*REG_PTR(insn, SH_RS1, regs))

#define GET_RS2(insn, regs)		(*REG_PTR(insn, SH_RS2, regs))

#define GET_RS1S(insn, regs)		(*REG_PTR(RVC_RS1S(insn), 0, regs))

#define GET_RS2S(insn, regs)		(*REG_PTR(RVC_RS2S(insn), 0, regs))

#define GET_RS2C(insn, regs)		(*REG_PTR(insn, SH_RS2C, regs))

#define GET_SP(regs)			(*REG_PTR(2, 0, regs))

#define SET_RD(insn, regs, val)		(*REG_PTR(insn, SH_RD, regs) = (val))

#define IMM_I(insn)			((s32)(insn) >> 20)

#define IMM_S(insn)			(((s32)(insn) >> 25 << 5) | \

					 (s32)(((insn) >> 7) & 0x1f))

#define MASK_FUNCT3			0x7000



#define GET_PRECISION(insn) (((insn) >> 25) & 3)

#define GET_RM(insn) (((insn) >> 12) & 7)

#define PRECISION_S 0

#define PRECISION_D 1



#ifdef CONFIG_FPU



#define FP_GET_RD(insn)		(insn >> 7 & 0x1F)

arch/riscv/kvm/vcpu_insn.c

+0 −126
Original line number Diff line number Diff line
@@ -10,132 +10,6 @@ 
#include <asm/cpufeature.h>

#include <asm/insn.h>



#define INSN_OPCODE_MASK	0x007c

#define INSN_OPCODE_SHIFT	2

#define INSN_OPCODE_SYSTEM	28



#define INSN_MASK_WFI		0xffffffff

#define INSN_MATCH_WFI		0x10500073



#define INSN_MASK_WRS		0xffffffff

#define INSN_MATCH_WRS		0x00d00073



#define INSN_MATCH_CSRRW	0x1073

#define INSN_MASK_CSRRW		0x707f

#define INSN_MATCH_CSRRS	0x2073

#define INSN_MASK_CSRRS		0x707f

#define INSN_MATCH_CSRRC	0x3073

#define INSN_MASK_CSRRC		0x707f

#define INSN_MATCH_CSRRWI	0x5073

#define INSN_MASK_CSRRWI	0x707f

#define INSN_MATCH_CSRRSI	0x6073

#define INSN_MASK_CSRRSI	0x707f

#define INSN_MATCH_CSRRCI	0x7073

#define INSN_MASK_CSRRCI	0x707f



#define INSN_MATCH_LB		0x3

#define INSN_MASK_LB		0x707f

#define INSN_MATCH_LH		0x1003

#define INSN_MASK_LH		0x707f

#define INSN_MATCH_LW		0x2003

#define INSN_MASK_LW		0x707f

#define INSN_MATCH_LD		0x3003

#define INSN_MASK_LD		0x707f

#define INSN_MATCH_LBU		0x4003

#define INSN_MASK_LBU		0x707f

#define INSN_MATCH_LHU		0x5003

#define INSN_MASK_LHU		0x707f

#define INSN_MATCH_LWU		0x6003

#define INSN_MASK_LWU		0x707f

#define INSN_MATCH_SB		0x23

#define INSN_MASK_SB		0x707f

#define INSN_MATCH_SH		0x1023

#define INSN_MASK_SH		0x707f

#define INSN_MATCH_SW		0x2023

#define INSN_MASK_SW		0x707f

#define INSN_MATCH_SD		0x3023

#define INSN_MASK_SD		0x707f



#define INSN_MATCH_C_LD		0x6000

#define INSN_MASK_C_LD		0xe003

#define INSN_MATCH_C_SD		0xe000

#define INSN_MASK_C_SD		0xe003

#define INSN_MATCH_C_LW		0x4000

#define INSN_MASK_C_LW		0xe003

#define INSN_MATCH_C_SW		0xc000

#define INSN_MASK_C_SW		0xe003

#define INSN_MATCH_C_LDSP	0x6002

#define INSN_MASK_C_LDSP	0xe003

#define INSN_MATCH_C_SDSP	0xe002

#define INSN_MASK_C_SDSP	0xe003

#define INSN_MATCH_C_LWSP	0x4002

#define INSN_MASK_C_LWSP	0xe003

#define INSN_MATCH_C_SWSP	0xc002

#define INSN_MASK_C_SWSP	0xe003



#define INSN_16BIT_MASK		0x3



#define INSN_IS_16BIT(insn)	(((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)



#define INSN_LEN(insn)		(INSN_IS_16BIT(insn) ? 2 : 4)



#ifdef CONFIG_64BIT

#define LOG_REGBYTES		3

#else

#define LOG_REGBYTES		2

#endif

#define REGBYTES		(1 << LOG_REGBYTES)



#define SH_RD			7

#define SH_RS1			15

#define SH_RS2			20

#define SH_RS2C			2

#define MASK_RX			0x1f



#define RVC_LW_IMM(x)		((RV_X(x, 6, 1) << 2) | \

				 (RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 5, 1) << 6))

#define RVC_LD_IMM(x)		((RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 5, 2) << 6))

#define RVC_LWSP_IMM(x)		((RV_X(x, 4, 3) << 2) | \

				 (RV_X(x, 12, 1) << 5) | \

				 (RV_X(x, 2, 2) << 6))

#define RVC_LDSP_IMM(x)		((RV_X(x, 5, 2) << 3) | \

				 (RV_X(x, 12, 1) << 5) | \

				 (RV_X(x, 2, 3) << 6))

#define RVC_SWSP_IMM(x)		((RV_X(x, 9, 4) << 2) | \

				 (RV_X(x, 7, 2) << 6))

#define RVC_SDSP_IMM(x)		((RV_X(x, 10, 3) << 3) | \

				 (RV_X(x, 7, 3) << 6))

#define RVC_RS1S(insn)		(8 + RV_X(insn, SH_RD, 3))

#define RVC_RS2S(insn)		(8 + RV_X(insn, SH_RS2C, 3))

#define RVC_RS2(insn)		RV_X(insn, SH_RS2C, 5)



#define SHIFT_RIGHT(x, y)		\

	((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))



#define REG_MASK			\

	((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))



#define REG_OFFSET(insn, pos)		\

	(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)



#define REG_PTR(insn, pos, regs)	\

	((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))



#define GET_FUNCT3(insn)	(((insn) >> 12) & 7)



#define GET_RS1(insn, regs)	(*REG_PTR(insn, SH_RS1, regs))

#define GET_RS2(insn, regs)	(*REG_PTR(insn, SH_RS2, regs))

#define GET_RS1S(insn, regs)	(*REG_PTR(RVC_RS1S(insn), 0, regs))

#define GET_RS2S(insn, regs)	(*REG_PTR(RVC_RS2S(insn), 0, regs))

#define GET_RS2C(insn, regs)	(*REG_PTR(insn, SH_RS2C, regs))

#define GET_SP(regs)		(*REG_PTR(2, 0, regs))

#define SET_RD(insn, regs, val)	(*REG_PTR(insn, SH_RD, regs) = (val))

#define IMM_I(insn)		((s32)(insn) >> 20)

#define IMM_S(insn)		(((s32)(insn) >> 25 << 5) | \

				 (s32)(((insn) >> 7) & 0x1f))



struct insn_func {

	unsigned long mask;

	unsigned long match;