Commit a60f627c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.20-2026-01-30' of... 

Merge tag 'amd-drm-next-6.20-2026-01-30' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-6.20-2026-01-30:

amdgpu:
- Misc cleanups
- SMU 13 fixes
- SMU 14 fixes
- GPUVM fault filter fix
- USB4 fixes
- DC FP guard fixes
- Powergating fix
- JPEG ring reset fix
- RAS fixes
- Xclk fix for soc21 APUs
- Fix COND_EXEC handling for GC 11
- UserQ fixes
- MQD size alignment fixes
- SMU feature interface cleanup
- GC 10-12 KGQ init fixes
- GC 11-12 KGQ reset fixes

amdkfd:
- Fix device snapshot reporting
- GC 12.1 trap handler fixes
- MQD size alignment fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260130183257.28879-1-alexander.deucher@amd.com
parents 502d2d8e 0a6d6ed6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+8 −0
Original line number Diff line number Diff line
@@ -1239,6 +1239,14 @@ struct amdgpu_device { 
	struct amdgpu_kfd_dev		kfd;

};



/*

 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t))

 * as fence address and writes a 32 bit fence value to this address.

 * Driver needs to allocate at least 4 DWs extra memory in addition to

 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety.

 */

#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))



static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,

					 uint8_t ip, uint8_t inst)

{

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

+3 −5
Original line number Diff line number Diff line
@@ -60,11 +60,9 @@ static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b) 
{

	const struct amdgpu_bo_list_entry *a = _a, *b = _b;



	if (a->priority > b->priority)

		return 1;

	if (a->priority < b->priority)

		return -1;

	return 0;

	BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX);



	return (int)a->priority - (int)b->priority;

}



int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+10 −8
Original line number Diff line number Diff line
@@ -385,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 
	struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];

	struct amdgpu_ring *ring = &kiq->ring;

	u32 domain = AMDGPU_GEM_DOMAIN_GTT;

	u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size);

	u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size);



#if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)

	/* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
@@ -424,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 
		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

			ring = &adev->gfx.gfx_ring[i];

			if (!ring->mqd_obj) {

				r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,

							    domain, &ring->mqd_obj,

				r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size),

								PAGE_SIZE, domain, &ring->mqd_obj,

							    &ring->mqd_gpu_addr, &ring->mqd_ptr);

				if (r) {

					dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);

					return r;

				}



				ring->mqd_size = mqd_size;

				ring->mqd_size = gfx_mqd_size;

				/* prepare MQD backup */

				adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL);

				adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL);

				if (!adev->gfx.me.mqd_backup[i]) {

					dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);

					return -ENOMEM;
@@ -448,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 
		j = i + xcc_id * adev->gfx.num_compute_rings;

		ring = &adev->gfx.compute_ring[j];

		if (!ring->mqd_obj) {

			r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,

						    domain, &ring->mqd_obj,

			r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size),

							PAGE_SIZE, domain, &ring->mqd_obj,

						    &ring->mqd_gpu_addr, &ring->mqd_ptr);

			if (r) {

				dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);

				return r;

			}



			ring->mqd_size = mqd_size;

			ring->mqd_size = compute_mqd_size;

			/* prepare MQD backup */

			adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL);

			adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL);

			if (!adev->gfx.mec.mqd_backup[j]) {

				dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);

				return -ENOMEM;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+6 −1
Original line number Diff line number Diff line
@@ -498,8 +498,13 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 


	if (adev->irq.retry_cam_enabled)

		return;



	else if (adev->irq.ih1.ring_size)

		ih = &adev->irq.ih1;

	else if (adev->irq.ih_soft.enabled)

		ih = &adev->irq.ih_soft;

	else

		return;



	/* Get the WPTR of the last entry in IH ring */

	last_wptr = amdgpu_ih_get_wptr(adev, ih);

	/* Order wptr with ring data. */

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+3 −2
Original line number Diff line number Diff line
@@ -235,7 +235,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 


	amdgpu_ring_ib_begin(ring);



	if (ring->funcs->emit_gfx_shadow)

	if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)

		amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,

					    init_shadow, vmid);
@@ -291,7 +291,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 
				       fence_flags | AMDGPU_FENCE_FLAG_64BIT);

	}



	if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {

	if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec &&

	    adev->gfx.cp_gfx_shadow) {

		amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);

		amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);

	}