Commit a69c1723 authored by Claudiu Manoil's avatar Claudiu Manoil Committed by Jakub Kicinski
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net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4 



For ENETC v4 these settings are controlled by the global ENETC
message and buffer cache attribute registers (EnBCAR and EnMCAR),
from the IERB register block.

The hardcoded cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: 99100d0d ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: default avatarWei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-2-claudiu.manoil@nxp.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 74d9391e

drivers/net/ethernet/freescale/enetc/enetc.c

+7 −4
Original line number Diff line number Diff line
@@ -2512,10 +2512,13 @@ int enetc_configure_si(struct enetc_ndev_priv *priv) 
	struct enetc_hw *hw = &si->hw;

	int err;



	if (is_enetc_rev1(si)) {

		/* set SI cache attributes */

		enetc_wr(hw, ENETC_SICAR0,

			 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);

		enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);

	}



	/* enable SI */

	enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);