Commit a6a7cba1 authored by Tianling Shen's avatar Tianling Shen Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: change eth phy mode to rgmii-id for orangepi r1 plus lts 



In general the delay should be added by the PHY instead of the MAC,
and this improves network stability on some boards which seem to
need different delay.

Fixes: 387b3bba ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
Cc: stable@vger.kernel.org # 6.6+
Signed-off-by: default avatarTianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20250119091154.1110762-1-cnsztl@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 5c8f9a05

arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

+1 −2
Original line number Diff line number Diff line
@@ -17,8 +17,7 @@ / { 


&gmac2io {

	phy-handle = <&yt8531c>;

	tx_delay = <0x19>;

	rx_delay = <0x05>;

	phy-mode = "rgmii-id";

	status = "okay";



	mdio {

arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ / { 


&gmac2io {

	phy-handle = <&rtl8211e>;

	phy-mode = "rgmii";

	tx_delay = <0x24>;

	rx_delay = <0x18>;

	status = "okay";

arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -109,7 +109,6 @@ &gmac2io { 
	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;

	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;

	clock_in_out = "input";

	phy-mode = "rgmii";

	phy-supply = <&vcc_io>;

	pinctrl-0 = <&rgmiim1_pins>;

	pinctrl-names = "default";