Commit a6b533ad authored by Huacai Chen's avatar Huacai Chen
Browse files

LoongArch: Don't panic if no valid cache info for PCI 



If there is no valid cache info detected (may happen in virtual machine)
for pci_dfl_cache_line_size, kernel shouldn't panic. Because in the PCI
core it will be evaluated to (L1_CACHE_BYTES >> 2).

Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 863a320d

arch/loongarch/pci/pci.c

+4 −4
Original line number Diff line number Diff line
@@ -50,11 +50,11 @@ static int __init pcibios_init(void) 
	 */

	lsize = cpu_last_level_cache_line_size();



	BUG_ON(!lsize);



	if (lsize) {

		pci_dfl_cache_line_size = lsize >> 2;



		pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);

	}



	return 0;

}