Commit a6ec1726 authored Oct 27, 2025 by Charlene Liu Committed by Alex Deucher Nov 18, 2025

drm/amd/display: Check DCCG_AUDIO_DTO2 register mask exist



[Why&How]
Check DCCG_AUDIO_DTO2 register mask exist before access.
Also,  add a existing DIO_CLOCK_control register for later use.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 8ffa289f

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1143,6 +1143,7 @@ void dce_aud_wall_dto_setup(
		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
		DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);

		if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO)
		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
		DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -227,7 +227,8 @@ void dcn401_prepare_mcache_programming(struct dc dc, struct dc_state context);
		#define LE_DCN401_REG_LIST_RI(id) \
		LE_DCN3_REG_LIST_RI(id), \
		SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \
		SRI_ARR(DIG_BE_CLK_CNTL, DIG, id)
		SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\
		SR_ARR(DIO_CLK_CNTL, id)

		/* DPP */
		#define DPP_REG_LIST_DCN401_COMMON_RI(id) \