Commit a7352c84 authored by Tomeu Vizoso's avatar Tomeu Vizoso Committed by Jeff Hugo
Browse files

dt-bindings: npu: rockchip,rknn: Add bindings 



Add the bindings for the Neural Processing Unit IP from Rockchip.

v2:
- Adapt to new node structure (one node per core, each with its own
  IOMMU)
- Several misc. fixes from Sebastian Reichel

v3:
- Split register block in its constituent subblocks, and only require
  the ones that the kernel would ever use (Nicolas Frattaroli)
- Group supplies (Rob Herring)
- Explain the way in which the top core is special (Rob Herring)

v4:
- Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski)
- Remove unneeded items: (Krzysztof Kozlowski)
- Fix use of minItems/maxItems (Krzysztof Kozlowski)
- Add reg-names to list of required properties (Krzysztof Kozlowski)
- Fix example (Krzysztof Kozlowski)

v5:
- Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski)
- Streamline compatible property (Krzysztof Kozlowski)

v6:
- Remove mention to NVDLA, as the hardware is only incidentally related
  (Kever Yang)
- Mark pclk and npu clocks as required by all clocks (Rob Herring)

v7:
- Remove allOf section, not needed now that all nodes require 4 clocks
  (Heiko Stübner)

v8:
- Remove notion of top core (Robin Murphy)

Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarTomeu Vizoso <tomeu@tomeuvizoso.net>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarJeff Hugo <jeff.hugo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-6-77ebd484941e@tomeuvizoso.net
parent 525ad89d

Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Neural Processing Unit IP from Rockchip



maintainers:

  - Tomeu Vizoso <tomeu@tomeuvizoso.net>



description:

  Rockchip IP for accelerating inference of neural networks.



  There is to be a node per each NPU core in the SoC, and each core should reference all the

  resources that it needs to function, such as clocks, power domains, and resets.



properties:

  $nodename:

    pattern: '^npu@[a-f0-9]+$'



  compatible:

    enum:

      - rockchip,rk3588-rknn-core



  reg:

    maxItems: 3



  reg-names:

    items:

      - const: pc # Program Control-related registers

      - const: cna # Convolution Neural Network Accelerator registers

      - const: core # Main NPU core processing unit registers



  clocks:

    maxItems: 4



  clock-names:

    items:

      - const: aclk

      - const: hclk

      - const: npu

      - const: pclk



  interrupts:

    maxItems: 1



  iommus:

    maxItems: 1



  npu-supply: true



  power-domains:

    maxItems: 1



  resets:

    maxItems: 2



  reset-names:

    items:

      - const: srst_a

      - const: srst_h



  sram-supply: true



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - interrupts

  - iommus

  - power-domains

  - resets

  - reset-names

  - npu-supply

  - sram-supply



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/rockchip,rk3588-cru.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/rk3588-power.h>

    #include <dt-bindings/reset/rockchip,rk3588-cru.h>



    bus {

      #address-cells = <2>;

      #size-cells = <2>;



      npu@fdab0000 {

        compatible = "rockchip,rk3588-rknn-core";

        reg = <0x0 0xfdab0000 0x0 0x1000>,

              <0x0 0xfdab1000 0x0 0x1000>,

              <0x0 0xfdab3000 0x0 0x1000>;

        reg-names = "pc", "cna", "core";

        clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,

                 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;

        clock-names = "aclk", "hclk", "npu", "pclk";

        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;

        iommus = <&rknn_mmu_0>;

        npu-supply = <&vdd_npu_s0>;

        power-domains = <&power RK3588_PD_NPUTOP>;

        resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;

        reset-names = "srst_a", "srst_h";

        sram-supply = <&vdd_npu_mem_s0>;

      };

    };

...