Commit a760b101 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - rockchip phy kconfig dependency fix with USB_COMMON and regression
   fix for old DT

 - stm32 phy overflow assertion fix

 - exonysfs phy refclk masks fix and power gate on exit fix

 - freescale fix for clock dividor valid range

 - TI regmap syscon register fix

 - tegra reset registers on init fix

* tag 'phy-fixes-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: tegra: xusb: reset VBUS & ID OVERRIDE
  phy: ti: gmii-sel: Do not use syscon helper to build regmap
  phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()
  phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to valid range
  phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk
  phy: stm32: Fix constant-value overflow assertion
  phy: rockchip: naneng-combphy: compatible reset with old DT
  phy: rockchip: fix Kconfig dependency more
parents 1973160c 55f1a5f7

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

+11 −2
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) 
	return container_of(hw, struct fsl_samsung_hdmi_phy, hw);

}



static void

static int

fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,

					    const struct phy_config *cfg)

{
@@ -341,6 +341,9 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, 
			break;

	}



	if (unlikely(div == 4))

		return -EINVAL;



	writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));



	/*
@@ -364,6 +367,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, 
	       FIELD_PREP(REG14_RP_CODE_MASK, 2) |

	       FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),

	       phy->regs + PHY_REG(14));



	return 0;

}



static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s)
@@ -466,7 +471,11 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, 
	writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK,

	       cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));



	fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);

	ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);

	if (ret) {

		dev_err(phy->dev, "pixclock too large\n");

		return ret;

	}



	writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));

drivers/phy/rockchip/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ config PHY_ROCKCHIP_USBDP 
	depends on ARCH_ROCKCHIP && OF

	depends on TYPEC

	select GENERIC_PHY

	select USB_COMMON

	help

	  Enable this to support the Rockchip USB3.0/DP combo PHY with

	  Samsung IP block. This is required for USB3 support on RK3588.

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

+4 −1
Original line number Diff line number Diff line
@@ -324,7 +324,10 @@ static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy 


	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");



	priv->phy_rst = devm_reset_control_get(dev, "phy");

	priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");

	/* fallback to old behaviour */

	if (PTR_ERR(priv->phy_rst) == -ENOENT)

		priv->phy_rst = devm_reset_control_array_get_exclusive(dev);

	if (IS_ERR(priv->phy_rst))

		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");

drivers/phy/samsung/phy-exynos5-usbdrd.c

+14 −11
Original line number Diff line number Diff line
@@ -488,9 +488,9 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) 
	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;



	/* FSEL settings corresponding to reference clock */

	reg &= ~PHYCLKRST_FSEL_PIPE_MASK |

	reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |

		 PHYCLKRST_MPLL_MULTIPLIER_MASK |

		PHYCLKRST_SSC_REFCLKSEL_MASK;

		 PHYCLKRST_SSC_REFCLKSEL_MASK);

	switch (phy_drd->extrefclk) {

	case EXYNOS5_FSEL_50MHZ:

		reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
@@ -532,9 +532,9 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) 
	reg &= ~PHYCLKRST_REFCLKSEL_MASK;

	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;



	reg &= ~PHYCLKRST_FSEL_UTMI_MASK |

	reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |

		 PHYCLKRST_MPLL_MULTIPLIER_MASK |

		PHYCLKRST_SSC_REFCLKSEL_MASK;

		 PHYCLKRST_SSC_REFCLKSEL_MASK);

	reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);



	return reg;
@@ -1296,14 +1296,17 @@ static int exynos5_usbdrd_gs101_phy_exit(struct phy *phy) 
	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);

	int ret;



	if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI)

		return 0;



	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {

		ret = exynos850_usbdrd_phy_exit(phy);

		if (ret)

			return ret;

	}



	exynos5_usbdrd_phy_isol(inst, true);



	if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI)

		return 0;



	return regulator_bulk_disable(phy_drd->drv_data->n_regulators,

				      phy_drd->regulators);

}

drivers/phy/st/phy-stm32-combophy.c

+18 −20
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static const struct clk_impedance imp_lookup[] = { 
	{ 4204000, { 511000, 609000, 706000, 802000 } },

	{ 3999000, { 571000, 648000, 726000, 803000 } }

};

#define DEFAULT_IMP_INDEX 3 /* Default impedance is 50 Ohm */



static int stm32_impedance_tune(struct stm32_combophy *combophy)

{
@@ -119,10 +120,9 @@ static int stm32_impedance_tune(struct stm32_combophy *combophy) 
	u8 imp_of, vswing_of;

	u32 max_imp = imp_lookup[0].microohm;

	u32 min_imp = imp_lookup[imp_size - 1].microohm;

	u32 max_vswing = imp_lookup[imp_size - 1].vswing[vswing_size - 1];

	u32 max_vswing;

	u32 min_vswing = imp_lookup[0].vswing[0];

	u32 val;

	u32 regval;



	if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) {

		if (val < min_imp || val > max_imp) {
@@ -130,45 +130,43 @@ static int stm32_impedance_tune(struct stm32_combophy *combophy) 
			return -EINVAL;

		}



		regval = 0;

		for (imp_of = 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++) {

			if (imp_lookup[imp_of].microohm <= val) {

				regval = FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of);

		for (imp_of = 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++)

			if (imp_lookup[imp_of].microohm <= val)

				break;

			}

		}



		if (WARN_ON(imp_of == ARRAY_SIZE(imp_lookup)))

			return -EINVAL;



		dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n",

			imp_lookup[imp_of].microohm);



		regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,

				   STM32MP25_PCIEPRG_IMPCTRL_OHM,

				   regval);

	} else {

		regmap_read(combophy->regmap, SYSCFG_PCIEPRGCR, &val);

		imp_of = FIELD_GET(STM32MP25_PCIEPRG_IMPCTRL_OHM, val);

	}

				   FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of));

	} else

		imp_of = DEFAULT_IMP_INDEX;



	if (!of_property_read_u32(combophy->dev->of_node, "st,output-vswing-microvolt", &val)) {

		max_vswing = imp_lookup[imp_of].vswing[vswing_size - 1];



		if (val < min_vswing || val > max_vswing) {

			dev_err(combophy->dev, "Invalid value %u for output vswing\n", val);

			return -EINVAL;

		}



		regval = 0;

		for (vswing_of = 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing); vswing_of++) {

			if (imp_lookup[imp_of].vswing[vswing_of] >= val) {

				regval = FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of);

		for (vswing_of = 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing); vswing_of++)

			if (imp_lookup[imp_of].vswing[vswing_of] >= val)

				break;

			}

		}



		if (WARN_ON(vswing_of == ARRAY_SIZE(imp_lookup[imp_of].vswing)))

			return -EINVAL;



		dev_dbg(combophy->dev, "Set %u microvolt swing\n",

			 imp_lookup[imp_of].vswing[vswing_of]);



		regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,

				   STM32MP25_PCIEPRG_IMPCTRL_VSWING,

				   regval);

				   FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of));

	}



	return 0;