Commit a7dc87f3 authored by Timur Kristóf's avatar Timur Kristóf Committed by Alex Deucher
Browse files

drm/amd/display: Properly disable scaling on DCE6 



SCL_SCALER_ENABLE can be used to enable/disable the scaler
on DCE6. Program it to 0 when scaling isn't used, 1 when used.
Additionally, clear some other registers when scaling is
disabled and program the SCL_UPDATE register as recommended.

This fixes visible glitches for users whose BIOS sets up a
mode with scaling at boot, which DC was unable to clean up.

Fixes: b70aaf55 ("drm/amd/display: dce_transform: add DCE6 specific macros,functions")
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarTimur Kristóf <timur.kristof@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c0aa7cf4

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

+11 −4
Original line number Diff line number Diff line
@@ -154,10 +154,13 @@ static bool dce60_setup_scaling_configuration( 
	REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);



	if (data->taps.h_taps + data->taps.v_taps <= 2) {

		/* Set bypass */



		/* DCE6 has no SCL_MODE register, skip scale mode programming */

		/* Disable scaler functionality */

		REG_WRITE(SCL_SCALER_ENABLE, 0);



		/* Clear registers that can cause glitches even when the scaler is off */

		REG_WRITE(SCL_TAP_CONTROL, 0);

		REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);

		REG_WRITE(SCL_F_SHARP_CONTROL, 0);

		return false;

	}
@@ -165,7 +168,7 @@ static bool dce60_setup_scaling_configuration( 
			SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,

			SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);



	/* DCE6 has no SCL_MODE register, skip scale mode programming */

	REG_WRITE(SCL_SCALER_ENABLE, 1);



	/* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels */
@@ -502,6 +505,8 @@ static void dce60_transform_set_scaler( 
	REG_SET(DC_LB_MEM_SIZE, 0,

		DC_LB_MEM_SIZE, xfm_dce->lb_memory_size);



	REG_WRITE(SCL_UPDATE, 0x00010000);



	/* Clear SCL_F_SHARP_CONTROL value to 0 */

	REG_WRITE(SCL_F_SHARP_CONTROL, 0);
@@ -564,6 +569,8 @@ static void dce60_transform_set_scaler( 
	/* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */



	/* DCE6 DATA_FORMAT register does not support ALPHA_EN */



	REG_WRITE(SCL_UPDATE, 0);

}

#endif

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

+2 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ 
	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \

	SRI(VIEWPORT_START, SCL, id), \

	SRI(VIEWPORT_SIZE, SCL, id), \

	SRI(SCL_SCALER_ENABLE, SCL, id), \

	SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \

	SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \

	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
@@ -592,6 +593,7 @@ struct dce_transform_registers { 
	uint32_t SCL_VERT_FILTER_SCALE_RATIO;

	uint32_t SCL_HORZ_FILTER_INIT;

#if defined(CONFIG_DRM_AMD_DC_SI)

	uint32_t SCL_SCALER_ENABLE;

	uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;

	uint32_t SCL_HORZ_FILTER_INIT_CHROMA;

#endif