Commit a7f5b36b authored by Suresh Vankadara's avatar Suresh Vankadara Committed by Hans Verkuil
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media: qcom: camss: Add support for camss driver on sc7280 



Add support for the camss driver on the sc7280 soc.

Signed-off-by: default avatarSuresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: default avatarTrishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: default avatarVikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Signed-off-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
parent 3522673b

drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c

+5 −0
Original line number Diff line number Diff line
@@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, 
	u32 val;



	switch (csiphy->camss->res->version) {

	case CAMSS_7280:

		r = &lane_regs_sm8250[0][0];

		array_size = ARRAY_SIZE(lane_regs_sm8250[0]);

		break;

	case CAMSS_8250:

		r = &lane_regs_sm8250[0][0];

		array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
@@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) 
	bool ret = false;



	switch (version) {

	case CAMSS_7280:

	case CAMSS_8250:

	case CAMSS_8280XP:

	case CAMSS_845:

drivers/media/platform/qcom/camss/camss-csiphy.c

+5 −0
Original line number Diff line number Diff line
@@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = { 
	.formats = formats_8x96

};



const struct csiphy_formats csiphy_formats_sc7280 = {

	.nformats = ARRAY_SIZE(formats_sdm845),

	.formats = formats_sdm845

};



const struct csiphy_formats csiphy_formats_sdm845 = {

	.nformats = ARRAY_SIZE(formats_sdm845),

	.formats = formats_sdm845

drivers/media/platform/qcom/camss/camss-csiphy.h

+1 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); 


extern const struct csiphy_formats csiphy_formats_8x16;

extern const struct csiphy_formats csiphy_formats_8x96;

extern const struct csiphy_formats csiphy_formats_sc7280;

extern const struct csiphy_formats csiphy_formats_sdm845;



extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;

drivers/media/platform/qcom/camss/camss-vfe.c

+2 −0
Original line number Diff line number Diff line
@@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, 
		}

		break;

	case CAMSS_660:

	case CAMSS_7280:

	case CAMSS_8x96:

	case CAMSS_8250:

	case CAMSS_8280XP:
@@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) 
	int ret = 8;



	switch (vfe->camss->res->version) {

	case CAMSS_7280:

	case CAMSS_8250:

	case CAMSS_8280XP:

	case CAMSS_845:

drivers/media/platform/qcom/camss/camss.c

+319 −0
Original line number Diff line number Diff line
@@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = { 
	},

};



static const struct camss_subdev_resources csiphy_res_7280[] = {

	/* CSIPHY0 */

	{

		.regulators = { "vdda-phy", "vdda-pll" },



		.clock = { "csiphy0", "csiphy0_timer" },

		.clock_rate = { { 300000000, 400000000 },

				{ 300000000 } },

		.reg = { "csiphy0" },

		.interrupt = { "csiphy0" },

		.csiphy = {

			.hw_ops = &csiphy_ops_3ph_1_0,

			.formats = &csiphy_formats_sc7280

		}

	},

	/* CSIPHY1 */

	{

		.regulators = { "vdda-phy", "vdda-pll" },



		.clock = { "csiphy1", "csiphy1_timer" },

		.clock_rate = { { 300000000, 400000000 },

				{ 300000000 } },

		.reg = { "csiphy1" },

		.interrupt = { "csiphy1" },

		.csiphy = {

			.hw_ops = &csiphy_ops_3ph_1_0,

			.formats = &csiphy_formats_sc7280

		}

	},

	/* CSIPHY2 */

	{

		.regulators = { "vdda-phy", "vdda-pll" },



		.clock = { "csiphy2", "csiphy2_timer" },

		.clock_rate = { { 300000000, 400000000 },

				{ 300000000 } },

		.reg = { "csiphy2" },

		.interrupt = { "csiphy2" },

		.csiphy = {

			.hw_ops = &csiphy_ops_3ph_1_0,

			.formats = &csiphy_formats_sc7280

		}

	},

	/* CSIPHY3 */

	{

		.regulators = { "vdda-phy", "vdda-pll" },



		.clock = { "csiphy3", "csiphy3_timer" },

		.clock_rate = { { 300000000, 400000000 },

				{ 300000000 } },

		.reg = { "csiphy3" },

		.interrupt = { "csiphy3" },

		.csiphy = {

			.hw_ops = &csiphy_ops_3ph_1_0,

			.formats = &csiphy_formats_sc7280

		}

	},

	/* CSIPHY4 */

	{

		.regulators = { "vdda-phy", "vdda-pll" },



		.clock = { "csiphy4", "csiphy4_timer" },

		.clock_rate = { { 300000000, 400000000 },

				{ 300000000 } },

		.reg = { "csiphy4" },

		.interrupt = { "csiphy4" },

		.csiphy = {

			.hw_ops = &csiphy_ops_3ph_1_0,

			.formats = &csiphy_formats_sc7280

		}

	},

};



static const struct camss_subdev_resources csid_res_7280[] = {

	/* CSID0 */

	{

		.regulators = {},



		.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },

		.clock_rate = { { 300000000, 400000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 }

		},



		.reg = { "csid0" },

		.interrupt = { "csid0" },

		.csid = {

			.is_lite = false,

			.hw_ops = &csid_ops_gen2,

			.parent_dev_ops = &vfe_parent_dev_ops,

			.formats = &csid_formats_gen2

		}

	},

	/* CSID1 */

	{

		.regulators = {},



		.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },

		.clock_rate = { { 300000000, 400000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 }

		},



		.reg = { "csid1" },

		.interrupt = { "csid1" },

		.csid = {

			.is_lite = false,

			.hw_ops = &csid_ops_gen2,

			.parent_dev_ops = &vfe_parent_dev_ops,

			.formats = &csid_formats_gen2

		}

	},

	/* CSID2 */

	{

		.regulators = {},



		.clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },

		.clock_rate = { { 300000000, 400000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 }

		},



		.reg = { "csid2" },

		.interrupt = { "csid2" },

		.csid = {

			.is_lite = false,

			.hw_ops = &csid_ops_gen2,

			.parent_dev_ops = &vfe_parent_dev_ops,

			.formats = &csid_formats_gen2

		}

	},

	/* CSID3 */

	{

		.regulators = {},



		.clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },

		.clock_rate = { { 300000000, 400000000 },

				{ 0 },

				{ 320000000, 400000000, 480000000, 600000000 }

		},



		.reg = { "csid_lite0" },

		.interrupt = { "csid_lite0" },

		.csid = {

			.is_lite = true,

			.hw_ops = &csid_ops_gen2,

			.parent_dev_ops = &vfe_parent_dev_ops,

			.formats = &csid_formats_gen2

		}

	},

	/* CSID4 */

	{

		.regulators = {},



		.clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },

		.clock_rate = { { 300000000, 400000000 },

				{ 0 },

				{ 320000000, 400000000, 480000000, 600000000 }

		},



		.reg = { "csid_lite1" },

		.interrupt = { "csid_lite1" },

		.csid = {

			.is_lite = true,

			.hw_ops = &csid_ops_gen2,

			.parent_dev_ops = &vfe_parent_dev_ops,

			.formats = &csid_formats_gen2

		}

	},

};



static const struct camss_subdev_resources vfe_res_7280[] = {

	/* VFE0 */

	{

		.regulators = {},



		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",

			   "vfe0_axi", "gcc_cam_hf_axi" },

		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },

				{ 80000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 },

				{ 0 },

				{ 0 } },



		.reg = { "vfe0" },

		.interrupt = { "vfe0" },

		.vfe = {

			.line_num = 3,

			.is_lite = false,

			.has_pd = true,

			.pd_name = "ife0",

			.hw_ops = &vfe_ops_170,

			.formats_rdi = &vfe_formats_rdi_845,

			.formats_pix = &vfe_formats_pix_845

		}

	},

	/* VFE1 */

	{

		.regulators = {},



		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",

			   "vfe1_axi", "gcc_cam_hf_axi" },

		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },

				{ 80000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 },

				{ 0 },

				{ 0 } },



		.reg = { "vfe1" },

		.interrupt = { "vfe1" },

		.vfe = {

			.line_num = 3,

			.is_lite = false,

			.has_pd = true,

			.pd_name = "ife1",

			.hw_ops = &vfe_ops_170,

			.formats_rdi = &vfe_formats_rdi_845,

			.formats_pix = &vfe_formats_pix_845

		}

	},

	/* VFE2 */

	{

		.regulators = {},



		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",

			   "vfe2_axi", "gcc_cam_hf_axi" },

		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },

				{ 80000000 },

				{ 0 },

				{ 380000000, 510000000, 637000000, 760000000 },

				{ 0 },

				{ 0 } },



		.reg = { "vfe2" },

		.interrupt = { "vfe2" },

		.vfe = {

			.line_num = 3,

			.is_lite = false,

			.hw_ops = &vfe_ops_170,

			.has_pd = true,

			.pd_name = "ife2",

			.formats_rdi = &vfe_formats_rdi_845,

			.formats_pix = &vfe_formats_pix_845

		}

	},

	/* VFE3 (lite) */

	{

		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",

			   "vfe_lite0", "gcc_cam_hf_axi" },

		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },

				{ 80000000 },

				{ 0 },

				{ 320000000, 400000000, 480000000, 600000000 },

				{ 0 } },



		.regulators = {},

		.reg = { "vfe_lite0" },

		.interrupt = { "vfe_lite0" },

		.vfe = {

			.line_num = 4,

			.is_lite = true,

			.hw_ops = &vfe_ops_170,

			.formats_rdi = &vfe_formats_rdi_845,

			.formats_pix = &vfe_formats_pix_845

		}

	},

	/* VFE4 (lite) */

	{

		.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",

			   "vfe_lite1", "gcc_cam_hf_axi" },

		.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },

				{ 80000000 },

				{ 0 },

				{ 320000000, 400000000, 480000000, 600000000 },

				{ 0 } },



		.regulators = {},

		.reg = { "vfe_lite1" },

		.interrupt = { "vfe_lite1" },

		.vfe = {

			.line_num = 4,

			.is_lite = true,

			.hw_ops = &vfe_ops_170,

			.formats_rdi = &vfe_formats_rdi_845,

			.formats_pix = &vfe_formats_pix_845

		}

	},

};



static const struct resources_icc icc_res_sc7280[] = {

	{

		.name = "ahb",

		.icc_bw_tbl.avg = 38400,

		.icc_bw_tbl.peak = 76800,

	},

	{

		.name = "hf_0",

		.icc_bw_tbl.avg = 2097152,

		.icc_bw_tbl.peak = 2097152,

	},

};



static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {

	/* CSIPHY0 */

	{
@@ -2685,10 +2989,25 @@ static const struct camss_resources sc8280xp_resources = { 
	.link_entities = camss_link_entities

};



static const struct camss_resources sc7280_resources = {

	.version = CAMSS_7280,

	.pd_name = "top",

	.csiphy_res = csiphy_res_7280,

	.csid_res = csid_res_7280,

	.vfe_res = vfe_res_7280,

	.icc_res = icc_res_sc7280,

	.icc_path_num = ARRAY_SIZE(icc_res_sc7280),

	.csiphy_num = ARRAY_SIZE(csiphy_res_7280),

	.csid_num = ARRAY_SIZE(csid_res_7280),

	.vfe_num = ARRAY_SIZE(vfe_res_7280),

	.link_entities = camss_link_entities

};



static const struct of_device_id camss_dt_match[] = {

	{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },

	{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },

	{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },

	{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },

	{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },

	{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },

	{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },